mirror of https://github.com/jeelabs/esp-link.git
Jeroen Domburg
10 years ago
parent
290fe32e46
commit
aef27aaa5b
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#############################################################
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# Required variables for each makefile
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# Discard this section from all parent makefiles
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# Expected variables (with automatic defaults):
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# CSRCS (all "C" files in the dir)
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# SUBDIRS (all subdirs with a Makefile)
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# GEN_LIBS - list of libs to be generated ()
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# GEN_IMAGES - list of images to be generated ()
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# COMPONENTS_xxx - a list of libs/objs in the form
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# subdir/lib to be extracted and rolled up into
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# a generated lib/image xxx.a ()
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#
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ifndef PDIR |
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GEN_LIBS = libdriver.a
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endif |
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#############################################################
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# Configuration i.e. compile options etc.
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# Target specific stuff (defines etc.) goes in here!
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# Generally values applying to a tree are captured in the
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# makefile at its root level - these are then overridden
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# for a subtree within the makefile rooted therein
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#
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#DEFINES +=
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#############################################################
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# Recursion Magic - Don't touch this!!
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#
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# Each subtree potentially has an include directory
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# corresponding to the common APIs applicable to modules
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# rooted at that subtree. Accordingly, the INCLUDE PATH
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# of a module can only contain the include directories up
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# its parent path, and not its siblings
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#
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# Required for each makefile to inherit from the parent
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#
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INCLUDES := $(INCLUDES) -I $(PDIR)include
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INCLUDES += -I ./
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PDIR := ../$(PDIR)
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sinclude $(PDIR)Makefile |
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@ -1,248 +0,0 @@ |
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/******************************************************************************
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* Copyright 2013-2014 Espressif Systems (Wuxi) |
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* |
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* FileName: uart.c |
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* |
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* Description: Two UART mode configration and interrupt handler. |
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* Check your hardware connection while use this mode. |
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* |
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* Modification history: |
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* 2014/3/12, v1.0 create this file. |
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*******************************************************************************/ |
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#include "espmissingincludes.h" |
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#include "ets_sys.h" |
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#include "osapi.h" |
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#include "driver/uart.h" |
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#include "driver/uart_register.h" |
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//#include "ssc.h"
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//#include "at.h"
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// UartDev is defined and initialized in rom code.
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extern UartDevice UartDev; |
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//extern os_event_t at_recvTaskQueue[at_recvTaskQueueLen];
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LOCAL void uart0_rx_intr_handler(void *para); |
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/******************************************************************************
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* FunctionName : uart_config |
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* Description : Internal used function |
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* UART0 used for data TX/RX, RX buffer size is 0x100, interrupt enabled |
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* UART1 just used for debug output |
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* Parameters : uart_no, use UART0 or UART1 defined ahead |
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* Returns : NONE |
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*******************************************************************************/ |
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LOCAL void ICACHE_FLASH_ATTR |
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uart_config(uint8 uart_no) |
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{ |
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if (uart_no == UART1) |
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{ |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK); |
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} |
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else |
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{ |
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/* rcv_buff size if 0x100 */ |
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ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rcv_buff)); |
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U); |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD); |
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// PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
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} |
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uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate)); |
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WRITE_PERI_REG(UART_CONF0(uart_no), UartDev.exist_parity |
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| UartDev.parity |
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| (UartDev.stop_bits << UART_STOP_BIT_NUM_S) |
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| (UartDev.data_bits << UART_BIT_NUM_S)); |
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//clear rx and tx fifo,not ready
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); |
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); |
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//set rx fifo trigger
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// WRITE_PERI_REG(UART_CONF1(uart_no),
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// ((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
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// ((96 & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S) |
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// UART_RX_FLOW_EN);
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if (uart_no == UART0) |
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{ |
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//set rx fifo trigger
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WRITE_PERI_REG(UART_CONF1(uart_no), |
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((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) | |
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((0x01 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | |
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UART_RX_FLOW_EN); |
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} |
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else |
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{ |
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WRITE_PERI_REG(UART_CONF1(uart_no), |
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((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S)); |
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} |
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//clear all interrupt
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WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff); |
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//enable rx_interrupt
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA); |
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} |
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/******************************************************************************
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* FunctionName : uart1_tx_one_char |
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* Description : Internal used function |
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* Use uart1 interface to transfer one char |
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* Parameters : uint8 TxChar - character to tx |
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* Returns : OK |
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*******************************************************************************/ |
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LOCAL STATUS |
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uart_tx_one_char(uint8 uart, uint8 TxChar) |
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{ |
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while (true) |
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{ |
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uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT<<UART_TXFIFO_CNT_S); |
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if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) { |
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break; |
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} |
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} |
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WRITE_PERI_REG(UART_FIFO(uart) , TxChar); |
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return OK; |
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} |
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/******************************************************************************
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* FunctionName : uart1_write_char |
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* Description : Internal used function |
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* Do some special deal while tx char is '\r' or '\n' |
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* Parameters : char c - character to tx |
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* Returns : NONE |
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*******************************************************************************/ |
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LOCAL void ICACHE_FLASH_ATTR |
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uart0_write_char(char c) |
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{ |
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if (c == '\n') |
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{ |
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uart_tx_one_char(UART0, '\r'); |
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uart_tx_one_char(UART0, '\n'); |
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} |
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else if (c == '\r') |
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{ |
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} |
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else |
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{ |
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uart_tx_one_char(UART0, c); |
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} |
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} |
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/******************************************************************************
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* FunctionName : uart0_tx_buffer |
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* Description : use uart0 to transfer buffer |
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* Parameters : uint8 *buf - point to send buffer |
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* uint16 len - buffer len |
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* Returns : |
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*******************************************************************************/ |
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void ICACHE_FLASH_ATTR |
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uart0_tx_buffer(uint8 *buf, uint16 len) |
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{ |
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uint16 i; |
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for (i = 0; i < len; i++) |
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{ |
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uart_tx_one_char(UART0, buf[i]); |
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} |
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} |
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/******************************************************************************
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* FunctionName : uart0_sendStr |
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* Description : use uart0 to transfer buffer |
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* Parameters : uint8 *buf - point to send buffer |
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* uint16 len - buffer len |
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* Returns : |
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*******************************************************************************/ |
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void ICACHE_FLASH_ATTR |
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uart0_sendStr(const char *str) |
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{ |
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while(*str) |
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{ |
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uart_tx_one_char(UART0, *str++); |
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} |
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} |
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/******************************************************************************
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* FunctionName : uart0_rx_intr_handler |
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* Description : Internal used function |
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* UART0 interrupt handler, add self handle code inside |
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* Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg |
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* Returns : NONE |
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*******************************************************************************/ |
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//extern void at_recvTask(void);
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LOCAL void |
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uart0_rx_intr_handler(void *para) |
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{ |
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/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
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* uart1 and uart0 respectively |
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*/ |
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// RcvMsgBuff *pRxBuff = (RcvMsgBuff *)para;
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// uint8 RcvChar;
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uint8 uart_no = UART0;//UartDev.buff_uart_no;
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// if (UART_RXFIFO_FULL_INT_ST != (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST))
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// {
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// return;
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// }
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if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) |
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{ |
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// at_recvTask();
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_FULL_INT_CLR); |
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} |
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// WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_FULL_INT_CLR);
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// if (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S))
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// {
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// RcvChar = READ_PERI_REG(UART_FIFO(uart_no)) & 0xFF;
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// at_recvTask();
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// *(pRxBuff->pWritePos) = RcvChar;
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// system_os_post(at_recvTaskPrio, NULL, RcvChar);
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// //insert here for get one command line from uart
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// if (RcvChar == '\r')
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// {
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// pRxBuff->BuffState = WRITE_OVER;
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// }
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//
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// pRxBuff->pWritePos++;
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//
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// if (pRxBuff->pWritePos == (pRxBuff->pRcvMsgBuff + RX_BUFF_SIZE))
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// {
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// // overflow ...we may need more error handle here.
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// pRxBuff->pWritePos = pRxBuff->pRcvMsgBuff ;
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// }
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// }
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} |
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/******************************************************************************
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* FunctionName : uart_init |
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* Description : user interface for init uart |
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* Parameters : UartBautRate uart0_br - uart0 bautrate |
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* UartBautRate uart1_br - uart1 bautrate |
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* Returns : NONE |
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*******************************************************************************/ |
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void ICACHE_FLASH_ATTR |
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uart_init(UartBautRate uart0_br, UartBautRate uart1_br) |
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{ |
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// rom use 74880 baut_rate, here reinitialize
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UartDev.baut_rate = uart0_br; |
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uart_config(UART0); |
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UartDev.baut_rate = uart1_br; |
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uart_config(UART1); |
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ETS_UART_INTR_ENABLE(); |
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// install uart0 putc callback
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os_install_putc1((void *)uart0_write_char); |
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} |
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void ICACHE_FLASH_ATTR |
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uart_reattach() |
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{ |
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uart_init(BIT_RATE_74880, BIT_RATE_74880); |
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// ETS_UART_INTR_ATTACH(uart_rx_intr_handler_ssc, &(UartDev.rcv_buff));
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// ETS_UART_INTR_ENABLE();
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} |
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@ -1,13 +0,0 @@ |
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<html><head><title>Test</title></head> |
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<body> |
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<p> |
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There's a LED. You can't see it, so it's no use clicking any of the buttons below. The buttons |
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do, however, turn the LED on and off. |
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</p> |
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<form method="post" action="led.cgi"> |
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<input type="submit" name="led" value="1"> |
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<input type="submit" name="led" value="0"> |
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</form> |
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</body></html> |
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@ -1,7 +0,0 @@ |
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<html> |
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<head><title>Test</title></head> |
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<body> |
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<h1>Test!</h1> |
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<p>Yay, the cpio filesystem thingy works. Click <a href="/test2.html">here</a> to see |
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if the 2nd page works too. |
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</p> |
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@ -1,12 +0,0 @@ |
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<html> |
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<head><title>Test</title></head> |
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<body> |
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<h1>Test2!</h1> |
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<p><b>New!</b>You can also control the <a href="led.html">LED</a>...</p> |
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<p>Here's an image of a cat (hopefully...)<br /> |
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<img src="cat.jpeg"><br /> |
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<img src="ceilingcat.jpg"><br /> |
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<img src="disapprove.jpg"><br /> |
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<img src="invisiblepogostick.jpg"><br /> |
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</p> |
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</body></html> |
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<html><head><title>Test</title></head> |
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<body> |
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<form method="post" action="test.cgi"> |
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<input type="text" name="Test1" value="t1"> |
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<input type="text" name="Test2" value="t2"> |
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<input type="submit" name="DoIt" value="Do It"> |
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</form> |
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</body></html> |
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@ -1,103 +0,0 @@ |
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#ifndef UART_APP_H |
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#define UART_APP_H |
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#include "uart_register.h" |
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#include "eagle_soc.h" |
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#include "c_types.h" |
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#define RX_BUFF_SIZE 256 |
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#define TX_BUFF_SIZE 100 |
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#define UART0 0 |
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#define UART1 1 |
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typedef enum { |
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FIVE_BITS = 0x0, |
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SIX_BITS = 0x1, |
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SEVEN_BITS = 0x2, |
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EIGHT_BITS = 0x3 |
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} UartBitsNum4Char; |
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typedef enum { |
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ONE_STOP_BIT = 0, |
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ONE_HALF_STOP_BIT = BIT2, |
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TWO_STOP_BIT = BIT2 |
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} UartStopBitsNum; |
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typedef enum { |
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NONE_BITS = 0, |
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ODD_BITS = 0, |
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EVEN_BITS = BIT4 |
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} UartParityMode; |
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typedef enum { |
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STICK_PARITY_DIS = 0, |
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STICK_PARITY_EN = BIT3 | BIT5 |
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} UartExistParity; |
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typedef enum { |
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BIT_RATE_9600 = 9600, |
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BIT_RATE_19200 = 19200, |
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BIT_RATE_38400 = 38400, |
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BIT_RATE_57600 = 57600, |
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BIT_RATE_74880 = 74880, |
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BIT_RATE_115200 = 115200, |
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BIT_RATE_230400 = 230400, |
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BIT_RATE_460800 = 460800, |
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BIT_RATE_921600 = 921600 |
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} UartBautRate; |
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typedef enum { |
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NONE_CTRL, |
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HARDWARE_CTRL, |
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XON_XOFF_CTRL |
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} UartFlowCtrl; |
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typedef enum { |
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EMPTY, |
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UNDER_WRITE, |
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WRITE_OVER |
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} RcvMsgBuffState; |
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typedef struct { |
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uint32 RcvBuffSize; |
|
||||||
uint8 *pRcvMsgBuff; |
|
||||||
uint8 *pWritePos; |
|
||||||
uint8 *pReadPos; |
|
||||||
uint8 TrigLvl; //JLU: may need to pad
|
|
||||||
RcvMsgBuffState BuffState; |
|
||||||
} RcvMsgBuff; |
|
||||||
|
|
||||||
typedef struct { |
|
||||||
uint32 TrxBuffSize; |
|
||||||
uint8 *pTrxBuff; |
|
||||||
} TrxMsgBuff; |
|
||||||
|
|
||||||
typedef enum { |
|
||||||
BAUD_RATE_DET, |
|
||||||
WAIT_SYNC_FRM, |
|
||||||
SRCH_MSG_HEAD, |
|
||||||
RCV_MSG_BODY, |
|
||||||
RCV_ESC_CHAR, |
|
||||||
} RcvMsgState; |
|
||||||
|
|
||||||
typedef struct { |
|
||||||
UartBautRate baut_rate; |
|
||||||
UartBitsNum4Char data_bits; |
|
||||||
UartExistParity exist_parity; |
|
||||||
UartParityMode parity; // chip size in byte
|
|
||||||
UartStopBitsNum stop_bits; |
|
||||||
UartFlowCtrl flow_ctrl; |
|
||||||
RcvMsgBuff rcv_buff; |
|
||||||
TrxMsgBuff trx_buff; |
|
||||||
RcvMsgState rcv_state; |
|
||||||
int received; |
|
||||||
int buff_uart_no; //indicate which uart use tx/rx buffer
|
|
||||||
} UartDevice; |
|
||||||
|
|
||||||
void uart_init(UartBautRate uart0_br, UartBautRate uart1_br); |
|
||||||
void uart0_sendStr(const char *str); |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
@ -1,128 +0,0 @@ |
|||||||
//Generated at 2012-07-03 18:44:06
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2010 - 2011 Espressif System |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef UART_REGISTER_H_INCLUDED |
|
||||||
#define UART_REGISTER_H_INCLUDED |
|
||||||
#define REG_UART_BASE( i ) (0x60000000+(i)*0xf00) |
|
||||||
//version value:32'h062000
|
|
||||||
|
|
||||||
#define UART_FIFO( i ) (REG_UART_BASE( i ) + 0x0) |
|
||||||
#define UART_RXFIFO_RD_BYTE 0x000000FF |
|
||||||
#define UART_RXFIFO_RD_BYTE_S 0 |
|
||||||
|
|
||||||
#define UART_INT_RAW( i ) (REG_UART_BASE( i ) + 0x4) |
|
||||||
#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) |
|
||||||
#define UART_BRK_DET_INT_RAW (BIT(7)) |
|
||||||
#define UART_CTS_CHG_INT_RAW (BIT(6)) |
|
||||||
#define UART_DSR_CHG_INT_RAW (BIT(5)) |
|
||||||
#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) |
|
||||||
#define UART_FRM_ERR_INT_RAW (BIT(3)) |
|
||||||
#define UART_PARITY_ERR_INT_RAW (BIT(2)) |
|
||||||
#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) |
|
||||||
#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) |
|
||||||
|
|
||||||
#define UART_INT_ST( i ) (REG_UART_BASE( i ) + 0x8) |
|
||||||
#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) |
|
||||||
#define UART_BRK_DET_INT_ST (BIT(7)) |
|
||||||
#define UART_CTS_CHG_INT_ST (BIT(6)) |
|
||||||
#define UART_DSR_CHG_INT_ST (BIT(5)) |
|
||||||
#define UART_RXFIFO_OVF_INT_ST (BIT(4)) |
|
||||||
#define UART_FRM_ERR_INT_ST (BIT(3)) |
|
||||||
#define UART_PARITY_ERR_INT_ST (BIT(2)) |
|
||||||
#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) |
|
||||||
#define UART_RXFIFO_FULL_INT_ST (BIT(0)) |
|
||||||
|
|
||||||
#define UART_INT_ENA( i ) (REG_UART_BASE( i ) + 0xC) |
|
||||||
#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) |
|
||||||
#define UART_BRK_DET_INT_ENA (BIT(7)) |
|
||||||
#define UART_CTS_CHG_INT_ENA (BIT(6)) |
|
||||||
#define UART_DSR_CHG_INT_ENA (BIT(5)) |
|
||||||
#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) |
|
||||||
#define UART_FRM_ERR_INT_ENA (BIT(3)) |
|
||||||
#define UART_PARITY_ERR_INT_ENA (BIT(2)) |
|
||||||
#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) |
|
||||||
#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) |
|
||||||
|
|
||||||
#define UART_INT_CLR( i ) (REG_UART_BASE( i ) + 0x10) |
|
||||||
#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) |
|
||||||
#define UART_BRK_DET_INT_CLR (BIT(7)) |
|
||||||
#define UART_CTS_CHG_INT_CLR (BIT(6)) |
|
||||||
#define UART_DSR_CHG_INT_CLR (BIT(5)) |
|
||||||
#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) |
|
||||||
#define UART_FRM_ERR_INT_CLR (BIT(3)) |
|
||||||
#define UART_PARITY_ERR_INT_CLR (BIT(2)) |
|
||||||
#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) |
|
||||||
#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) |
|
||||||
|
|
||||||
#define UART_CLKDIV( i ) (REG_UART_BASE( i ) + 0x14) |
|
||||||
#define UART_CLKDIV_CNT 0x000FFFFF |
|
||||||
#define UART_CLKDIV_S 0 |
|
||||||
|
|
||||||
#define UART_AUTOBAUD( i ) (REG_UART_BASE( i ) + 0x18) |
|
||||||
#define UART_GLITCH_FILT 0x000000FF |
|
||||||
#define UART_GLITCH_FILT_S 8 |
|
||||||
#define UART_AUTOBAUD_EN (BIT(0)) |
|
||||||
|
|
||||||
#define UART_STATUS( i ) (REG_UART_BASE( i ) + 0x1C) |
|
||||||
#define UART_TXD (BIT(31)) |
|
||||||
#define UART_RTSN (BIT(30)) |
|
||||||
#define UART_DTRN (BIT(29)) |
|
||||||
#define UART_TXFIFO_CNT 0x000000FF |
|
||||||
#define UART_TXFIFO_CNT_S 16 |
|
||||||
#define UART_RXD (BIT(15)) |
|
||||||
#define UART_CTSN (BIT(14)) |
|
||||||
#define UART_DSRN (BIT(13)) |
|
||||||
#define UART_RXFIFO_CNT 0x000000FF |
|
||||||
#define UART_RXFIFO_CNT_S 0 |
|
||||||
|
|
||||||
#define UART_CONF0( i ) (REG_UART_BASE( i ) + 0x20) |
|
||||||
#define UART_TXFIFO_RST (BIT(18)) |
|
||||||
#define UART_RXFIFO_RST (BIT(17)) |
|
||||||
#define UART_IRDA_EN (BIT(16)) |
|
||||||
#define UART_TX_FLOW_EN (BIT(15)) |
|
||||||
#define UART_LOOPBACK (BIT(14)) |
|
||||||
#define UART_IRDA_RX_INV (BIT(13)) |
|
||||||
#define UART_IRDA_TX_INV (BIT(12)) |
|
||||||
#define UART_IRDA_WCTL (BIT(11)) |
|
||||||
#define UART_IRDA_TX_EN (BIT(10)) |
|
||||||
#define UART_IRDA_DPLX (BIT(9)) |
|
||||||
#define UART_TXD_BRK (BIT(8)) |
|
||||||
#define UART_SW_DTR (BIT(7)) |
|
||||||
#define UART_SW_RTS (BIT(6)) |
|
||||||
#define UART_STOP_BIT_NUM 0x00000003 |
|
||||||
#define UART_STOP_BIT_NUM_S 4 |
|
||||||
#define UART_BIT_NUM 0x00000003 |
|
||||||
#define UART_BIT_NUM_S 2 |
|
||||||
#define UART_PARITY_EN (BIT(1)) |
|
||||||
#define UART_PARITY (BIT(0)) |
|
||||||
|
|
||||||
#define UART_CONF1( i ) (REG_UART_BASE( i ) + 0x24) |
|
||||||
#define UART_RX_TOUT_EN (BIT(31)) |
|
||||||
#define UART_RX_TOUT_THRHD 0x0000007F |
|
||||||
#define UART_RX_TOUT_THRHD_S 24 |
|
||||||
#define UART_RX_FLOW_EN (BIT(23)) |
|
||||||
#define UART_RX_FLOW_THRHD 0x0000007F |
|
||||||
#define UART_RX_FLOW_THRHD_S 16 |
|
||||||
#define UART_TXFIFO_EMPTY_THRHD 0x0000007F |
|
||||||
#define UART_TXFIFO_EMPTY_THRHD_S 8 |
|
||||||
#define UART_RXFIFO_FULL_THRHD 0x0000007F |
|
||||||
#define UART_RXFIFO_FULL_THRHD_S 0 |
|
||||||
|
|
||||||
#define UART_LOWPULSE( i ) (REG_UART_BASE( i ) + 0x28) |
|
||||||
#define UART_LOWPULSE_MIN_CNT 0x000FFFFF |
|
||||||
#define UART_LOWPULSE_MIN_CNT_S 0 |
|
||||||
|
|
||||||
#define UART_HIGHPULSE( i ) (REG_UART_BASE( i ) + 0x2C) |
|
||||||
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF |
|
||||||
#define UART_HIGHPULSE_MIN_CNT_S 0 |
|
||||||
|
|
||||||
#define UART_PULSE_NUM( i ) (REG_UART_BASE( i ) + 0x30) |
|
||||||
#define UART_PULSE_NUM_CNT 0x0003FF |
|
||||||
#define UART_PULSE_NUM_CNT_S 0 |
|
||||||
|
|
||||||
#define UART_DATE( i ) (REG_UART_BASE( i ) + 0x78) |
|
||||||
#define UART_ID( i ) (REG_UART_BASE( i ) + 0x7C) |
|
||||||
#endif // UART_REGISTER_H_INCLUDED
|
|
||||||
@ -1,5 +1,10 @@ |
|||||||
|
|
||||||
CFLAGS=-I../lib/heatshrink -std=gnu99
|
CFLAGS=-I../lib/heatshrink -std=gnu99
|
||||||
|
OBJS=main.o heatshrink_encoder.o
|
||||||
|
TARGET=mkespfsimage
|
||||||
|
|
||||||
mkespfsimage: main.o heatshrink_encoder.o |
$(TARGET): $(OBJS) |
||||||
$(CC) -o $@ $^
|
$(CC) -o $@ $^
|
||||||
|
|
||||||
|
clean: |
||||||
|
rm -f $(TARGET) $(OBJS)
|
||||||
Loading…
Reference in new issue