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@ -420,21 +420,18 @@ bool AudioControlES8388_F32::enable(TwoWire *i2cBus, uint8_t addr, config_t cfg) |
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ctrlBus = i2cBus; |
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ctrlBus = i2cBus; |
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i2cAddr = addr; |
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i2cAddr = addr; |
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ctrlBus->begin(); |
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ctrlBus->begin(); |
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ctrlBus->setClock(100000); |
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ctrlBus->setClock(100000);
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bool reply = true; |
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if (!writeReg(ES8388_REG_MASTER_MODE_CTRL, 0x00)) // set to slave mode
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reply = writeReg(ES8388_REG_MASTER_MODE_CTRL, 0x00); // set to slave mode
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reply &= writeReg(ES8388_REG_CHIP_PWR_MAN, 0xF3); // power down
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reply &=writeReg(ES8388_REG_DAC_CTRL21, ES8388_BIT_SLRCK); // DACLRC = ADCLRC
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reply &=writeReg(ES8388_REG_CHIP_CTRL1, ES8388_VMIDSEL_5K | ES8388_BIT_ENREF); // 50k divider,
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reply &=writeReg(ES8388_REG_CHIP_CTRL2, 0x40); // low power modes off, bit6 not defined? based on default value
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reply &=writeReg(ES8388_REG_ADC_PWR_MAN, 0x00); // power up ADC, turn off the PDNMICB?
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reply &=writeReg(ES8388_REG_DAC_PWR_MAN, ES8388_BIT_LOUT1_EN | ES8388_BIT_ROUT1_EN); // enable LR1
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if (reply == false) |
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{ |
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{ |
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DBG_SERIAL.println("Codec i2c error"); |
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return false; // codec not found
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return false; |
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}
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} |
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writeReg(ES8388_REG_CHIP_PWR_MAN, 0xF3); // power down
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writeReg(ES8388_REG_DAC_CTRL21, ES8388_BIT_SLRCK); // DACLRC = ADCLRC
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writeReg(ES8388_REG_CHIP_CTRL1, ES8388_VMIDSEL_5K | ES8388_BIT_ENREF); // 50k divider,
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writeReg(ES8388_REG_CHIP_CTRL2, 0x40); // low power modes off, bit6 not defined? based on default value
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writeReg(ES8388_REG_ADC_PWR_MAN, 0x00); // power up ADC, turn off the PDNMICB?
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writeReg(ES8388_REG_DAC_PWR_MAN, ES8388_BIT_LOUT1_EN | ES8388_BIT_ROUT1_EN); // enable LR1
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switch (cfg) |
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switch (cfg) |
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{ |
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{ |
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case ES8388_CFG_LINEIN_DIFF: |
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case ES8388_CFG_LINEIN_DIFF: |
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@ -479,7 +476,7 @@ bool AudioControlES8388_F32::enable(TwoWire *i2cBus, uint8_t addr, config_t cfg) |
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optimizeConversion(0); |
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optimizeConversion(0); |
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writeReg(ES8388_REG_CHIP_PWR_MAN, 0x00); // Power up DEM and STM
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writeReg(ES8388_REG_CHIP_PWR_MAN, 0x00); // Power up DEM and STM
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// ALC config
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// ALC config - disabled for now, will be tested someday..
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// writeReg(ES8388_REG_ADC_CTRL10, ES8388_ALCSEL(ES8388_ALCSEL_LR) | // ALC OFF
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// writeReg(ES8388_REG_ADC_CTRL10, ES8388_ALCSEL(ES8388_ALCSEL_LR) | // ALC OFF
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// ES8388_MAXGAIN(ES8388_MAXGAIN_M0_5DB) | // max gain -0.5dB
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// ES8388_MAXGAIN(ES8388_MAXGAIN_M0_5DB) | // max gain -0.5dB
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// ES8388_MINGAIN(ES8388_MINGAIN_M12DB)); // min gain -12dB
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// ES8388_MINGAIN(ES8388_MINGAIN_M12DB)); // min gain -12dB
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@ -555,7 +552,6 @@ uint8_t AudioControlES8388_F32::getInGain() |
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void AudioControlES8388_F32::set_noiseGate(float thres) |
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void AudioControlES8388_F32::set_noiseGate(float thres) |
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{ |
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{ |
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uint8_t thres_val = constrain(thres, 0.0f, 1.0f) * 31.99f; |
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uint8_t thres_val = constrain(thres, 0.0f, 1.0f) * 31.99f; |
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DBG_SERIAL.printf("Gate: %d\r\n", thres_val); |
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writeReg(ES8388_REG_ADC_CTRL14, ES8388_NGTH(thres_val) | ES8388_NGG(ES8388_NGG_ADCMUTE)| ES8388_BIT_NGAT_EN);
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writeReg(ES8388_REG_ADC_CTRL14, ES8388_NGTH(thres_val) | ES8388_NGG(ES8388_NGG_ADCMUTE)| ES8388_BIT_NGAT_EN);
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} |
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} |
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