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205 lines
6.7 KiB
205 lines
6.7 KiB
3 months ago
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/**
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* @file control_AK4452_F32.cpp
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* @author Piotr Zapart
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* @brief driver for the AK4452 DAC
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* @version 0.1
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* @date 2024-06-14
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*
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* @copyright Copyright (c) 2024 www.hexefx.com
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* This program is free software: you can redistribute it and/or modify it under
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* the terms of the GNU General Public License as published by the Free Software Foundation,
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* either version 3 of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along with this program.
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* If not, see <https://www.gnu.org/licenses/>."
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*/
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#include "control_AK4452_F32.h"
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#define AK4452_REG_CTRL1 (0x00)
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#define AK4452_REG_CTRL1_DFLT (0x0C)
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#define AK4452_BIT_RSTN (1<<0)
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#define AK4452_DIF_MASK (0x0E)
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#define AK4452_DIF_SHIFT (0x01)
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#define AK4452_DIF(x) (((x)<<AK4452_DIF_SHIFT)&AK4452_DIF_MASK)
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#define AK4452_DIF_16B_LSB (0x00)
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#define AK4452_DIF_20B_LSB (0x01)
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#define AK4452_DIF_24B_MSB (0x02)
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#define AK4452_DIF_24B_I2S (0x03)
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#define AK4452_DIF_24B_LSB (0x04)
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#define AK4452_DIF_32B_LSB (0x05)
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#define AK4452_DIF_32B_MSB (0x06)
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#define AK4452_DIF_32B_I2S (0x07)
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#define AK4452_BIT_ACKS (1<<7)
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#define AK4452_REG_CTRL2 (0x01)
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#define AK4452_REG_CTRL2_DFLT (0x22)
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#define AK4452_BIT_SMUTE (1<<0)
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#define AK4452_DEM_MASK (0x06)
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#define AK4452_DEM_SHIFT (0x01)
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#define AK4452_DEM(x) (((x)<<AK4452_DEM_SHIFT)&AK4452_DEM_MASK)
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#define AK4452_DEM_44_1K (0x00)
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#define AK4452_DEM_OFF (0x01)
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#define AK4452_DEM_48K (0x02)
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#define AK4452_DEM_32K (0x03)
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#define AK4452_DFS10_MASK (0x18)
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#define AK4452_DFS10_SHIFT (0x03)
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#define AK4452_DFS10(x) (((x)<<AK4452_DFS10_SHIFT)&AK4452_DFS10_MASK)
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#define AK4452_DFS_NORMAL (0x00)
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#define AK4452_DFS_DOUBLE (0x01)
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#define AK4452_DFS_QUAD (0x02)
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#define AK4452_DFS_OCT (0x04)
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#define AK4452_DFS_HEX (0x05)
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#define AK4452_BIT_SD (1<<5)
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#define AK4452_REG_CTRL3 (0x02)
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#define AK4452_REG_CTRL3_DFLT (0x00)
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#define AK4452_BIT_SLOW (1<<0)
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#define AK4452_BIT_SELLR1 (1<<1)
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#define AK4452_BIT_DZFB (1<<2)
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#define AK4452_BIT_MONO1 (1<<3)
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#define AK4452_BIT_DCKB (1<<4)
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#define AK4452_BIT_DCKS (1<<5)
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#define AK4452_BIT_DP (1<<7)
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#define AK4452_REG_L1CH_ATT (0x03)
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#define AK4452_REG_L1CH_ATT_DFLT (0xFF)
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#define AK4452_REG_R1CH_ATT (0x04)
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#define AK4452_REG_R1CH_ATT_DFLT (0xFF)
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#define AK4452_REG_CTRL4 (0x05)
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#define AK4452_REG_CTRL4_DFLT (0x00)
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#define AK4452_BIT_SSLOW (1<<0)
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#define AK4452_DFS2_MASK (1<<1)
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#define AK4452_DFS2_SHIFT (0x01)
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#define AK4452_DFS2(x) (((x)<<AK4452_DFS2_SHIFT)&AK4452_DFS2_MASK) // bits10 in CTRL2
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#define AK4452_BIT_INVL1 (1<<6)
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#define AK4452_BIT_INVR1 (1<<7)
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#define AK4452_REG_DSD1 (0x06)
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#define AK4452_REG_DSD1_DFLT (0x00)
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#define AK4452_BIT_DSDSEL0 (1<<0)
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#define AK4452_BIT_DSDD (1<<1)
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#define AK4452_BIT_DMRE (1<<3)
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#define AK4452_BIT_DMC (1<<4)
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#define AK4452_BIT_DMR1 (1<<5)
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#define AK4452_BIT_DML1 (1<<6)
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#define AK4452_BIT_DDM (1<<7)
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#define AK4452_REG_CTRL5 (0x07)
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#define AK4452_REG_CTRL5_DFLT (0x03)
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#define AK4452_BIT_SYNCE (1<<0)
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#define AK4452_REG_SND_CTRL (0x08)
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#define AK4452_REG_SND_CTRL_DFLT (0x00)
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#define AK4452_SC_MASK (0x03)
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#define AK4452_SC_SHIFT (0x00)
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#define AK4452_SC(x) (((x)<<AK4452_SC_SHIFT)&AK4452_SC_MASK)
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#define AK4452_SC_NORMAL (0x00)
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#define AK4452_SC_MAX (0x01)
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#define AK4452_SC_MIN (0x02)
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#define AK4452_BIT_DZF_L1 (1<<6)
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#define AK4452_BIT_DZF_R1 (1<<7)
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#define AK4452_REG_DSD2 (0x09)
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#define AK4452_REG_DSD2_DFLT (0x00)
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#define AK4452_BIT_DSDSEL1 (1<<0)
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#define AK4452_BIT_DSDF (1<<1)
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#define AK4452_REG_CTRL6 (0x0A)
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#define AK4452_REG_CTRL6_DFLT (0x0D)
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#define AK4452_BIT_PW1 (1<<2)
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#define AK4452_SDS21_MASK (0x30)
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#define AK4452_SDS21_SHIFT (0x04)
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#define AK4452_SDS21(x) (((x)<<AK4452_SDS21_SHIFT)&AK4452_SDS21_MASK)
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#define AK4452_SDS_TDM128_L1R1 (0x00)
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#define AK4452_SDS_TDM128_L2R2 (0x01)
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#define AK4452_SDS_TDM256_L1R1 (0x00)
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#define AK4452_SDS_TDM256_L2R2 (0x01)
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#define AK4452_SDS_TDM256_L3R3 (0x02)
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#define AK4452_SDS_TDM256_L4R4 (0x03)
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#define AK4452_SDS_TDM512_L1R1 (0x00)
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#define AK4452_SDS_TDM512_L2R2 (0x01)
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#define AK4452_SDS_TDM512_L3R3 (0x02)
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#define AK4452_SDS_TDM512_L4R4 (0x03)
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#define AK4452_SDS_TDM512_L5R5 (0x04)
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#define AK4452_SDS_TDM512_L6R6 (0x05)
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#define AK4452_SDS_TDM512_L7R7 (0x06)
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#define AK4452_SDS_TDM512_L8R8 (0x07)
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#define AK4452_TDM_MASK (0xC0)
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#define AK4452_TDM_SHIFT (0x06)
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#define AK4452_TDM(x) (((x)<<AK4452_TDM_SHIFT)&AK4452_TDM_MASK)
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#define AK4452_TDM_NORMAL (0x00)
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#define AK4452_TDM_128 (0x01)
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#define AK4452_TDM_246 (0x02)
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#define AK4452_TDM_512 (0x03)
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#define AK4452_REG_CTRL7 (0x0B)
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#define AK4452_REG_CTRL7_DFLT (0x0C)
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#define AK4452_BIT_DCHAIN (1<<2)
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#define AK4452_SDS0_MASK (1<<4)
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#define AK4452_SDS0_SHIFT (0x04)
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#define AK4452_SDS0(x) (((x)<<AK4452_SDS0_SHIFT)&AK4452_SDS0_MASK)
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#define AK4452_ATS_MASK (0xC0)
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#define AK4452_ATS_SHIFT (0x06)
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#define AK4452_ATS(x) (((x)<<AK4452_ATS_SHIFT)&AK4452_ATS_MASK)
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#define AK4452_ATS_4080 (0x00)
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#define AK4452_ATS_2040 (0x01)
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#define AK4452_ATS_510 (0x02)
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#define AK4452_ATS_255 (0x03)
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#define AK4452_REG_CTRL8 (0x0C)
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#define AK4452_REG_CTRL8_DFLT (0x00)
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#define AK4452_FIR(x) ((x)&0x07)
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bool AudioControlAK4452_F32::configured = false;
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bool AudioControlAK4452_F32::enable(TwoWire *i2cBus, uint8_t addr)
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{
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ctrlBus = i2cBus;
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i2cAddr = addr;
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ctrlBus->begin();
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ctrlBus->setClock(400000);
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if (!writeReg(AK4452_REG_CTRL1, 0x00)) // put the registers in reset mode
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{
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return false; // codec not found
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}
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// DIF[2:0] = 0b111 - 32bit I2S, Normal mode
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// DFS[2:0] = 0b000 (default) Normal speed mode
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// DSDSEL[1:0] = 0b10 256fs
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writeReg(AK4452_REG_DSD2, AK4452_BIT_DSDSEL1);
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writeReg(AK4452_REG_CTRL1, AK4452_DIF(AK4452_DIF_32B_I2S) | AK4452_BIT_RSTN);
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configured = true;
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return true;
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}
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bool AudioControlAK4452_F32::writeReg(uint8_t addr, uint8_t val)
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{
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ctrlBus->beginTransmission(i2cAddr);
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ctrlBus->write(addr);
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ctrlBus->write(val);
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return ctrlBus->endTransmission() == 0;
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}
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bool AudioControlAK4452_F32::readReg(uint8_t addr, uint8_t *valPtr)
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{
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ctrlBus->beginTransmission(i2cAddr);
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ctrlBus->write(addr);
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if (ctrlBus->endTransmission(false) != 0)
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return false;
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if (ctrlBus->requestFrom((int)i2cAddr, 1) < 1) return false;
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*valPtr = ctrlBus->read();
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return true;
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}
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uint8_t AudioControlAK4452_F32::modifyReg(uint8_t reg, uint8_t val, uint8_t iMask)
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{
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uint8_t val1;
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val1 = (readReg(reg, &val1) & (~iMask)) | val;
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if (!writeReg(reg, val1))
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return 0;
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return val1;
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}
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