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@ -62,7 +62,7 @@ uart_config(uint8 uart_no) |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, 0); // FUNC_U0RXD==0
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} |
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uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate)); |
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uart_div_modify(uart_no, UART_CLK_FREQ / UartDev.baut_rate); |
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if (uart_no == UART1) //UART 1 always 8 N 1
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WRITE_PERI_REG(UART_CONF0(uart_no), |
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@ -77,19 +77,20 @@ uart_config(uint8 uart_no) |
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if (uart_no == UART0) { |
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// Configure RX interrupt conditions as follows: trigger rx-full when there are 80 characters
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// in the buffer (allows for 64-byte HEX records), trigger rx-timeout when the fifo is
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// non-empty and nothing further has been received for 4 character period. Also set the
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// hardware flow-control to trigger when the FIFO holds 100 characters, although we don't
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// really expect the signals to actually be wired up to anything. It doesn't hurt to set
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// the threshold here...
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// in the buffer, trigger rx-timeout when the fifo is non-empty and nothing further has been
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// received for 4 character periods.
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// Set the hardware flow-control to trigger when the FIFO holds 100 characters, although
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// we don't really expect the signals to actually be wired up to anything. It doesn't hurt
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// to set the threshold here...
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// We do not enable framing error interrupts 'cause they tend to cause an interrupt avalanche
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// and instead just poll for them when we get a std RX interrupt.
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WRITE_PERI_REG(UART_CONF1(uart_no), |
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((80 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) | |
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((100 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | |
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UART_RX_FLOW_EN | |
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(4 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S | |
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UART_RX_TOUT_EN); |
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | |
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UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA); |
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); |
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} else { |
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WRITE_PERI_REG(UART_CONF1(uart_no), |
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((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S)); |
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@ -169,7 +170,7 @@ uart0_sendStr(const char *str) |
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} |
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} |
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static bool rx_bad; // set to true on framing error to avoid printing errors continuously
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static uint32 last_frm_err; // time in us when last framing error message was printed
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/******************************************************************************
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* FunctionName : uart0_rx_intr_handler |
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@ -181,33 +182,32 @@ static bool rx_bad; // set to true on framing error to avoid printing errors con |
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static void // must not use ICACHE_FLASH_ATTR !
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uart0_rx_intr_handler(void *para) |
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{ |
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/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2,
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* bit0 represents uart1 and uart0 respectively */ |
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uint8 uart_no = UART0;//UartDev.buff_uart_no;
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// we assume that uart1 has interrupts disabled (it uses the same interrupt vector)
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uint8 uart_no = UART0; |
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const uint32 one_sec = 1000000; // one second in usecs
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if(UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST)) |
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{ |
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if (!rx_bad) os_printf("FRM_ERR\n"); |
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rx_bad = true; |
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//clear rx and tx fifo
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// we end up largely ignoring framing errors and we just print a warning every second max
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if (READ_PERI_REG(UART_INT_RAW(uart_no)) & UART_FRM_ERR_INT_RAW) { |
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uint32 now = system_get_time(); |
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if (last_frm_err == 0 || (now - last_frm_err) > one_sec) { |
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os_printf("UART framing error (bad baud rate?)\n"); |
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last_frm_err = now; |
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} |
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// clear rx fifo (apparently this is not optional at this point)
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST); |
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST); |
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// reset interrupt
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR); |
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// reset framing error
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_FRM_ERR_INT_CLR); |
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// once framing errors are gone for 10 secs we forget about having seen them
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} else if (last_frm_err != 0 && (system_get_time() - last_frm_err) > 10*one_sec) { |
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last_frm_err = 0; |
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} |
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if(UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) |
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if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST) |
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|| UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)) |
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{ |
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//os_printf("fifo fullr\n");
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ETS_UART_INTR_DISABLE(); |
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system_os_post(recvTaskPrio, 0, 0); |
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} |
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else if(UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)) |
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{ |
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rx_bad = false; |
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ETS_UART_INTR_DISABLE(); |
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//os_printf("stat:%02X",*(uint8 *)UART_INT_ENA(uart_no));
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ETS_UART_INTR_DISABLE(); |
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system_os_post(recvTaskPrio, 0, 0); |
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} |
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} |
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@ -241,6 +241,7 @@ uart_recvTask(os_event_t *events) |
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void ICACHE_FLASH_ATTR |
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uart0_baud(int rate) { |
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os_printf("UART %d baud\n", rate); |
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uart_div_modify(UART0, UART_CLK_FREQ / rate); |
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} |
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