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231 lines
8.1 KiB
231 lines
8.1 KiB
// ---------------------------------------------------------------------------
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// This file is part of reSID, a MOS6581 SID emulator engine.
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// Copyright (C) 2004 Dag Lem <resid@nimrod.no>
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ---------------------------------------------------------------------------
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#define __ENVELOPE_CC__
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#include "envelope.h"
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RESID_NAMESPACE_START
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// ----------------------------------------------------------------------------
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// Constructor.
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// ----------------------------------------------------------------------------
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EnvelopeGenerator::EnvelopeGenerator()
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{
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reset();
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}
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// ----------------------------------------------------------------------------
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// SID reset.
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// ----------------------------------------------------------------------------
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void EnvelopeGenerator::reset()
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{
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envelope_counter = 0;
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attack = 0;
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decay = 0;
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sustain = 0;
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release = 0;
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gate = 0;
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rate_counter = 0;
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exponential_counter = 0;
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exponential_counter_period = 1;
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state = RELEASE;
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rate_period = rate_counter_period[release];
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hold_zero = true;
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}
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// Rate counter periods are calculated from the Envelope Rates table in
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// the Programmer's Reference Guide. The rate counter period is the number of
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// cycles between each increment of the envelope counter.
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// The rates have been verified by sampling ENV3.
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//
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// The rate counter is a 16 bit register which is incremented each cycle.
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// When the counter reaches a specific comparison value, the envelope counter
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// is incremented (attack) or decremented (decay/release) and the
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// counter is zeroed.
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//
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// NB! Sampling ENV3 shows that the calculated values are not exact.
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// It may seem like most calculated values have been rounded (.5 is rounded
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// down) and 1 has beed added to the result. A possible explanation for this
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// is that the SID designers have used the calculated values directly
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// as rate counter comparison values, not considering a one cycle delay to
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// zero the counter. This would yield an actual period of comparison value + 1.
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//
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// The time of the first envelope count can not be exactly controlled, except
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// possibly by resetting the chip. Because of this we cannot do cycle exact
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// sampling and must devise another method to calculate the rate counter
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// periods.
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//
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// The exact rate counter periods can be determined e.g. by counting the number
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// of cycles from envelope level 1 to envelope level 129, and dividing the
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// number of cycles by 128. CIA1 timer A and B in linked mode can perform
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// the cycle count. This is the method used to find the rates below.
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//
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// To avoid the ADSR delay bug, sampling of ENV3 should be done using
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// sustain = release = 0. This ensures that the attack state will not lower
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// the current rate counter period.
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//
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// The ENV3 sampling code below yields a maximum timing error of 14 cycles.
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// lda #$01
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// l1: cmp $d41c
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// bne l1
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// ...
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// lda #$ff
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// l2: cmp $d41c
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// bne l2
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//
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// This yields a maximum error for the calculated rate period of 14/128 cycles.
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// The described method is thus sufficient for exact calculation of the rate
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// periods.
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//
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const reg16 EnvelopeGenerator::rate_counter_period[] = {
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9, // 2ms*1.0MHz/256 = 7.81
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32, // 8ms*1.0MHz/256 = 31.25
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63, // 16ms*1.0MHz/256 = 62.50
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95, // 24ms*1.0MHz/256 = 93.75
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149, // 38ms*1.0MHz/256 = 148.44
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220, // 56ms*1.0MHz/256 = 218.75
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267, // 68ms*1.0MHz/256 = 265.63
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313, // 80ms*1.0MHz/256 = 312.50
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392, // 100ms*1.0MHz/256 = 390.63
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977, // 250ms*1.0MHz/256 = 976.56
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1954, // 500ms*1.0MHz/256 = 1953.13
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3126, // 800ms*1.0MHz/256 = 3125.00
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3907, // 1 s*1.0MHz/256 = 3906.25
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11720, // 3 s*1.0MHz/256 = 11718.75
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19532, // 5 s*1.0MHz/256 = 19531.25
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31251 // 8 s*1.0MHz/256 = 31250.00
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};
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// For decay and release, the clock to the envelope counter is sequentially
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// divided by 1, 2, 4, 8, 16, 30, 1 to create a piece-wise linear approximation
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// of an exponential. The exponential counter period is loaded at the envelope
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// counter values 255, 93, 54, 26, 14, 6, 0. The period can be different for the
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// same envelope counter value, depending on whether the envelope has been
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// rising (attack -> release) or sinking (decay/release).
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//
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// Since it is not possible to reset the rate counter (the test bit has no
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// influence on the envelope generator whatsoever) a method must be devised to
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// do cycle exact sampling of ENV3 to do the investigation. This is possible
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// with knowledge of the rate period for A=0, found above.
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//
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// The CPU can be synchronized with ENV3 by first synchronizing with the rate
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// counter by setting A=0 and wait in a carefully timed loop for the envelope
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// counter _not_ to change for 9 cycles. We can then wait for a specific value
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// of ENV3 with another timed loop to fully synchronize with ENV3.
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//
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// At the first period when an exponential counter period larger than one
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// is used (decay or relase), one extra cycle is spent before the envelope is
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// decremented. The envelope output is then delayed one cycle until the state
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// is changed to attack. Now one cycle less will be spent before the envelope
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// is incremented, and the situation is normalized.
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// The delay is probably caused by the comparison with the exponential counter,
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// and does not seem to affect the rate counter. This has been verified by
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// timing 256 consecutive complete envelopes with A = D = R = 1, S = 0, using
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// CIA1 timer A and B in linked mode. If the rate counter is not affected the
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// period of each complete envelope is
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// (255 + 162*1 + 39*2 + 28*4 + 12*8 + 8*16 + 6*30)*32 = 756*32 = 32352
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// which corresponds exactly to the timed value divided by the number of
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// complete envelopes.
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// NB! This one cycle delay is not modeled.
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// From the sustain levels it follows that both the low and high 4 bits of the
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// envelope counter are compared to the 4-bit sustain value.
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// This has been verified by sampling ENV3.
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//
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const reg8 EnvelopeGenerator::sustain_level[] = {
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0x00,
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0x11,
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0x22,
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0x33,
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0x44,
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0x55,
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0x66,
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0x77,
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0x88,
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0x99,
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0xaa,
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0xbb,
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0xcc,
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0xdd,
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0xee,
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0xff,
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};
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// ----------------------------------------------------------------------------
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// Register functions.
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// ----------------------------------------------------------------------------
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void EnvelopeGenerator::writeCONTROL_REG(reg8 control)
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{
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reg8 gate_next = control & 0x01;
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// The rate counter is never reset, thus there will be a delay before the
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// envelope counter starts counting up (attack) or down (release).
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// Gate bit on: Start attack, decay, sustain.
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if (!gate && gate_next) {
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state = ATTACK;
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rate_period = rate_counter_period[attack];
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// Switching to attack state unlocks the zero freeze.
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hold_zero = false;
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}
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// Gate bit off: Start release.
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else if (gate && !gate_next) {
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state = RELEASE;
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rate_period = rate_counter_period[release];
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}
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gate = gate_next;
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}
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void EnvelopeGenerator::writeATTACK_DECAY(reg8 attack_decay)
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{
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attack = (attack_decay >> 4) & 0x0f;
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decay = attack_decay & 0x0f;
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if (state == ATTACK) {
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rate_period = rate_counter_period[attack];
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}
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else if (state == DECAY_SUSTAIN) {
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rate_period = rate_counter_period[decay];
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}
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}
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void EnvelopeGenerator::writeSUSTAIN_RELEASE(reg8 sustain_release)
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{
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sustain = (sustain_release >> 4) & 0x0f;
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release = sustain_release & 0x0f;
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if (state == RELEASE) {
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rate_period = rate_counter_period[release];
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}
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}
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reg8 EnvelopeGenerator::readENV()
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{
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return output();
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}
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RESID_NAMESPACE_STOP
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