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535 lines
14 KiB
535 lines
14 KiB
// ---------------------------------------------------------------------------
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// This file is part of reSID, a MOS6581 SID emulator engine.
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// Copyright (C) 2004 Dag Lem <resid@nimrod.no>
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ---------------------------------------------------------------------------
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#ifndef __FILTER_H__
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#define __FILTER_H__
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#include "siddefs.h"
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#include "spline.h"
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RESID_NAMESPACE_START
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// ----------------------------------------------------------------------------
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// The SID filter is modeled with a two-integrator-loop biquadratic filter,
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// which has been confirmed by Bob Yannes to be the actual circuit used in
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// the SID chip.
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//
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// Measurements show that excellent emulation of the SID filter is achieved,
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// except when high resonance is combined with high sustain levels.
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// In this case the SID op-amps are performing less than ideally and are
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// causing some peculiar behavior of the SID filter. This however seems to
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// have more effect on the overall amplitude than on the color of the sound.
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//
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// The theory for the filter circuit can be found in "Microelectric Circuits"
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// by Adel S. Sedra and Kenneth C. Smith.
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// The circuit is modeled based on the explanation found there except that
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// an additional inverter is used in the feedback from the bandpass output,
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// allowing the summer op-amp to operate in single-ended mode. This yields
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// inverted filter outputs with levels independent of Q, which corresponds with
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// the results obtained from a real SID.
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//
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// We have been able to model the summer and the two integrators of the circuit
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// to form components of an IIR filter.
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// Vhp is the output of the summer, Vbp is the output of the first integrator,
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// and Vlp is the output of the second integrator in the filter circuit.
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//
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// According to Bob Yannes, the active stages of the SID filter are not really
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// op-amps. Rather, simple NMOS inverters are used. By biasing an inverter
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// into its region of quasi-linear operation using a feedback resistor from
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// input to output, a MOS inverter can be made to act like an op-amp for
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// small signals centered around the switching threshold.
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//
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// Qualified guesses at SID filter schematics are depicted below.
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//
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// SID filter
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// ----------
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//
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// -----------------------------------------------
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// | |
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// | ---Rq-- |
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// | | | |
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// | ------------<A]-----R1--------- |
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// | | | |
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// | | ---C---| ---C---|
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// | | | | | |
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// | --R1-- ---R1-- |---Rs--| |---Rs--|
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// | | | | | | | |
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// ----R1--|-----[A>--|--R-----[A>--|--R-----[A>--|
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// | | | |
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// vi -----R1-- | | |
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//
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// vhp vbp vlp
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//
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//
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// vi - input voltage
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// vhp - highpass output
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// vbp - bandpass output
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// vlp - lowpass output
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// [A> - op-amp
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// R1 - summer resistor
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// Rq - resistor array controlling resonance (4 resistors)
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// R - NMOS FET voltage controlled resistor controlling cutoff frequency
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// Rs - shunt resitor
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// C - capacitor
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//
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//
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//
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// SID integrator
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// --------------
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//
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// V+
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//
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// |
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// |
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// -----|
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// | |
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// | ||--
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// -||
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// ---C--- ||->
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// | | |
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// |---Rs-----------|---- vo
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// | |
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// | ||--
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// vi ---- -----|------------||
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// | ^ | ||->
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// |___| | |
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// ----- | |
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// | | |
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// |---R2-- |
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// |
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// R1 V-
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// |
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// |
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//
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// Vw
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//
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// ----------------------------------------------------------------------------
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class Filter
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{
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public:
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Filter();
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void enable_filter(bool enable);
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// void set_chip_model(chip_model model);
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RESID_INLINE
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void clock(sound_sample voice1, sound_sample voice2, sound_sample voice3,
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sound_sample ext_in);
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RESID_INLINE
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void clock(cycle_count delta_t,
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sound_sample voice1, sound_sample voice2, sound_sample voice3,
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sound_sample ext_in);
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void reset();
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// Write registers.
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void writeFC_LO(reg8);
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void writeFC_HI(reg8);
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void writeRES_FILT(reg8);
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void writeMODE_VOL(reg8);
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// SID audio output (16 bits).
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sound_sample output();
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// Spline functions.
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void fc_default(const fc_point*& points, int& count);
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PointPlotter<sound_sample> fc_plotter();
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protected:
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void set_w0();
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void set_Q();
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// Filter enabled.
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bool enabled;
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// Filter cutoff frequency.
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reg12 fc;
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// Filter resonance.
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reg8 res;
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// Selects which inputs to route through filter.
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reg8 filt;
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// Switch voice 3 off.
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reg8 voice3off;
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// Highpass, bandpass, and lowpass filter modes.
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reg8 hp_bp_lp;
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// Output master volume.
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reg4 vol;
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// Mixer DC offset.
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sound_sample mixer_DC;
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// State of filter.
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sound_sample Vhp; // highpass
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sound_sample Vbp; // bandpass
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sound_sample Vlp; // lowpass
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sound_sample Vnf; // not filtered
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// Cutoff frequency, resonance.
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sound_sample w0, w0_ceil_1, w0_ceil_dt;
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sound_sample _1024_div_Q;
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// Cutoff frequency tables.
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// FC is an 11 bit register.
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sound_sample f0_6581[2048];
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//sound_sample f0_8580[2048];
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sound_sample* f0;
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const static fc_point f0_points_6581[];
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//const static fc_point f0_points_8580[];
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const fc_point* f0_points;
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int f0_count;
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friend class SID;
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};
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// ----------------------------------------------------------------------------
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// Inline functions.
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// The following functions are defined inline because they are called every
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// time a sample is calculated.
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// ----------------------------------------------------------------------------
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#if RESID_INLINING || defined(__FILTER_CC__)
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// ----------------------------------------------------------------------------
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// SID clocking - 1 cycle.
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// ----------------------------------------------------------------------------
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RESID_INLINE
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void Filter::clock(sound_sample voice1,
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sound_sample voice2,
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sound_sample voice3,
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sound_sample ext_in)
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{
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// Scale each voice down from 20 to 13 bits.
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voice1 >>= 7;
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voice2 >>= 7;
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// NB! Voice 3 is not silenced by voice3off if it is routed through
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// the filter.
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if (voice3off && !(filt & 0x04)) {
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voice3 = 0;
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}
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else {
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voice3 >>= 7;
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}
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ext_in >>= 7;
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// This is handy for testing.
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if (!enabled) {
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Vnf = voice1 + voice2 + voice3 + ext_in;
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Vhp = Vbp = Vlp = 0;
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return;
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}
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// Route voices into or around filter.
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// The code below is expanded to a switch for faster execution.
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// (filt1 ? Vi : Vnf) += voice1;
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// (filt2 ? Vi : Vnf) += voice2;
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// (filt3 ? Vi : Vnf) += voice3;
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sound_sample Vi;
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switch (filt) {
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default:
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case 0x0:
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Vi = 0;
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Vnf = voice1 + voice2 + voice3 + ext_in;
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break;
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case 0x1:
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Vi = voice1;
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Vnf = voice2 + voice3 + ext_in;
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break;
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case 0x2:
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Vi = voice2;
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Vnf = voice1 + voice3 + ext_in;
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break;
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case 0x3:
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Vi = voice1 + voice2;
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Vnf = voice3 + ext_in;
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break;
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case 0x4:
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Vi = voice3;
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Vnf = voice1 + voice2 + ext_in;
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break;
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case 0x5:
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Vi = voice1 + voice3;
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Vnf = voice2 + ext_in;
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break;
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case 0x6:
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Vi = voice2 + voice3;
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Vnf = voice1 + ext_in;
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break;
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case 0x7:
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Vi = voice1 + voice2 + voice3;
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Vnf = ext_in;
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break;
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case 0x8:
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Vi = ext_in;
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Vnf = voice1 + voice2 + voice3;
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break;
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case 0x9:
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Vi = voice1 + ext_in;
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Vnf = voice2 + voice3;
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break;
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case 0xa:
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Vi = voice2 + ext_in;
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Vnf = voice1 + voice3;
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break;
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case 0xb:
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Vi = voice1 + voice2 + ext_in;
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Vnf = voice3;
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break;
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case 0xc:
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Vi = voice3 + ext_in;
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Vnf = voice1 + voice2;
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break;
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case 0xd:
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Vi = voice1 + voice3 + ext_in;
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Vnf = voice2;
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break;
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case 0xe:
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Vi = voice2 + voice3 + ext_in;
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Vnf = voice1;
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break;
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case 0xf:
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Vi = voice1 + voice2 + voice3 + ext_in;
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Vnf = 0;
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break;
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}
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// delta_t = 1 is converted to seconds given a 1MHz clock by dividing
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// with 1 000 000.
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// Calculate filter outputs.
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// Vhp = Vbp/Q - Vlp - Vi;
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// dVbp = -w0*Vhp*dt;
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// dVlp = -w0*Vbp*dt;
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sound_sample dVbp = (w0_ceil_1*Vhp >> 20);
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sound_sample dVlp = (w0_ceil_1*Vbp >> 20);
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Vbp -= dVbp;
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Vlp -= dVlp;
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Vhp = (Vbp*_1024_div_Q >> 10) - Vlp - Vi;
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}
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// ----------------------------------------------------------------------------
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// SID clocking - delta_t cycles.
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// ----------------------------------------------------------------------------
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RESID_INLINE
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void Filter::clock(cycle_count delta_t,
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sound_sample voice1,
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sound_sample voice2,
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sound_sample voice3,
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sound_sample ext_in)
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{
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// Scale each voice down from 20 to 13 bits.
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voice1 >>= 7;
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voice2 >>= 7;
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// NB! Voice 3 is not silenced by voice3off if it is routed through
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// the filter.
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if (voice3off && !(filt & 0x04)) {
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voice3 = 0;
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}
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else {
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voice3 >>= 7;
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}
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ext_in >>= 7;
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// Enable filter on/off.
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// This is not really part of SID, but is useful for testing.
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// On slow CPUs it may be necessary to bypass the filter to lower the CPU
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// load.
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if (!enabled) {
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Vnf = voice1 + voice2 + voice3 + ext_in;
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Vhp = Vbp = Vlp = 0;
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return;
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}
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// Route voices into or around filter.
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// The code below is expanded to a switch for faster execution.
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// (filt1 ? Vi : Vnf) += voice1;
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// (filt2 ? Vi : Vnf) += voice2;
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// (filt3 ? Vi : Vnf) += voice3;
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sound_sample Vi;
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switch (filt) {
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default:
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case 0x0:
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Vi = 0;
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Vnf = voice1 + voice2 + voice3 + ext_in;
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break;
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case 0x1:
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Vi = voice1;
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Vnf = voice2 + voice3 + ext_in;
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break;
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case 0x2:
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Vi = voice2;
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Vnf = voice1 + voice3 + ext_in;
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break;
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case 0x3:
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Vi = voice1 + voice2;
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Vnf = voice3 + ext_in;
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break;
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case 0x4:
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Vi = voice3;
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Vnf = voice1 + voice2 + ext_in;
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break;
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case 0x5:
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Vi = voice1 + voice3;
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Vnf = voice2 + ext_in;
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break;
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case 0x6:
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Vi = voice2 + voice3;
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Vnf = voice1 + ext_in;
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break;
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case 0x7:
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Vi = voice1 + voice2 + voice3;
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Vnf = ext_in;
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break;
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case 0x8:
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Vi = ext_in;
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Vnf = voice1 + voice2 + voice3;
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break;
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case 0x9:
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Vi = voice1 + ext_in;
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Vnf = voice2 + voice3;
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break;
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case 0xa:
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Vi = voice2 + ext_in;
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Vnf = voice1 + voice3;
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break;
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case 0xb:
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Vi = voice1 + voice2 + ext_in;
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Vnf = voice3;
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break;
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case 0xc:
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Vi = voice3 + ext_in;
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Vnf = voice1 + voice2;
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break;
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case 0xd:
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Vi = voice1 + voice3 + ext_in;
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Vnf = voice2;
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break;
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case 0xe:
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Vi = voice2 + voice3 + ext_in;
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Vnf = voice1;
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break;
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case 0xf:
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Vi = voice1 + voice2 + voice3 + ext_in;
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Vnf = 0;
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break;
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}
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// Maximum delta cycles for the filter to work satisfactorily under current
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// cutoff frequency and resonance constraints is approximately 8.
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cycle_count delta_t_flt = 8;
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while (delta_t) {
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if (delta_t < delta_t_flt) {
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delta_t_flt = delta_t;
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}
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// delta_t is converted to seconds given a 1MHz clock by dividing
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// with 1 000 000. This is done in two operations to avoid integer
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// multiplication overflow.
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// Calculate filter outputs.
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// Vhp = Vbp/Q - Vlp - Vi;
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// dVbp = -w0*Vhp*dt;
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// dVlp = -w0*Vbp*dt;
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sound_sample w0_delta_t = w0_ceil_dt * delta_t_flt >> 6;
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sound_sample dVbp = (w0_delta_t*Vhp >> 14);
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sound_sample dVlp = (w0_delta_t*Vbp >> 14);
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Vbp -= dVbp;
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Vlp -= dVlp;
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Vhp = (Vbp*_1024_div_Q >> 10) - Vlp - Vi;
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delta_t -= delta_t_flt;
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}
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}
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// ----------------------------------------------------------------------------
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// SID audio output (20 bits).
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// ----------------------------------------------------------------------------
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RESID_INLINE
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sound_sample Filter::output()
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{
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// This is handy for testing.
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if (!enabled) {
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return (Vnf + mixer_DC)*static_cast<sound_sample>(vol);
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}
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// Mix highpass, bandpass, and lowpass outputs. The sum is not
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// weighted, this can be confirmed by sampling sound output for
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// e.g. bandpass, lowpass, and bandpass+lowpass from a SID chip.
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// The code below is expanded to a switch for faster execution.
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// if (hp) Vf += Vhp;
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// if (bp) Vf += Vbp;
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// if (lp) Vf += Vlp;
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sound_sample Vf;
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switch (hp_bp_lp) {
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default:
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case 0x0:
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Vf = 0;
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break;
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case 0x1:
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Vf = Vlp;
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break;
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case 0x2:
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Vf = Vbp;
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break;
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case 0x3:
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Vf = Vlp + Vbp;
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break;
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case 0x4:
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Vf = Vhp;
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break;
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case 0x5:
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Vf = Vlp + Vhp;
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break;
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case 0x6:
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Vf = Vbp + Vhp;
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break;
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case 0x7:
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Vf = Vlp + Vbp + Vhp;
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break;
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}
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// Sum non-filtered and filtered output.
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// Multiply the sum with volume.
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return (Vnf + Vf + mixer_DC)*static_cast<sound_sample>(vol);
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}
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#endif // RESID_INLINING || defined(__FILTER_CC__)
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RESID_NAMESPACE_STOP
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#endif // not __FILTER_H__
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