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435 lines
13 KiB
435 lines
13 KiB
/* Audio Library for Teensy 3.X
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* Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
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*
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* Development of this audio library was funded by PJRC.COM, LLC by sales of
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* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop
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* open source software by purchasing Teensy or other PJRC products.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice, development funding notice, and this permission
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* notice shall be included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "output_i2s_f32.h"
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#include "memcpy_audio.h"
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#include <arm_math.h>
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audio_block_t * AudioOutputI2S_F32::block_left_1st = NULL;
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audio_block_t * AudioOutputI2S_F32::block_right_1st = NULL;
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audio_block_t * AudioOutputI2S_F32::block_left_2nd = NULL;
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audio_block_t * AudioOutputI2S_F32::block_right_2nd = NULL;
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uint16_t AudioOutputI2S_F32::block_left_offset = 0;
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uint16_t AudioOutputI2S_F32::block_right_offset = 0;
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bool AudioOutputI2S_F32::update_responsibility = false;
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DMAMEM static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
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DMAChannel AudioOutputI2S_F32::dma(false);
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void AudioOutputI2S_F32::begin(void)
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{
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dma.begin(true); // Allocate the DMA channel first
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block_left_1st = NULL;
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block_right_1st = NULL;
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// TODO: should we set & clear the I2S_TCSR_SR bit here?
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config_i2s();
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
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#if defined(KINETISK)
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dma.TCD->SADDR = i2s_tx_buffer;
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dma.TCD->SOFF = 2;
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
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dma.TCD->NBYTES_MLNO = 2;
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dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
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dma.TCD->DADDR = &I2S0_TDR0;
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dma.TCD->DOFF = 0;
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dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
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dma.TCD->DLASTSGA = 0;
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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
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#endif
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
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update_responsibility = update_setup();
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dma.enable();
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I2S0_TCSR = I2S_TCSR_SR;
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
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dma.attachInterrupt(isr);
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}
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void AudioOutputI2S_F32::isr(void)
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{
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#if defined(KINETISK)
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int16_t *dest;
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audio_block_t *blockL, *blockR;
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uint32_t saddr, offsetL, offsetR;
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saddr = (uint32_t)(dma.TCD->SADDR);
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dma.clearInterrupt();
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if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
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// DMA is transmitting the first half of the buffer
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// so we must fill the second half
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dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
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if (AudioOutputI2S_F32::update_responsibility) AudioStream_F32::update_all();
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} else {
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// DMA is transmitting the second half of the buffer
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// so we must fill the first half
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dest = (int16_t *)i2s_tx_buffer;
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}
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blockL = AudioOutputI2S_F32::block_left_1st;
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blockR = AudioOutputI2S_F32::block_right_1st;
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offsetL = AudioOutputI2S_F32::block_left_offset;
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offsetR = AudioOutputI2S_F32::block_right_offset;
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if (blockL && blockR) {
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memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR);
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offsetL += AUDIO_BLOCK_SAMPLES / 2;
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offsetR += AUDIO_BLOCK_SAMPLES / 2;
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} else if (blockL) {
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memcpy_tointerleaveL(dest, blockL->data + offsetL);
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offsetL += AUDIO_BLOCK_SAMPLES / 2;
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} else if (blockR) {
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memcpy_tointerleaveR(dest, blockR->data + offsetR);
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offsetR += AUDIO_BLOCK_SAMPLES / 2;
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} else {
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memset(dest,0,AUDIO_BLOCK_SAMPLES * 2);
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return;
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}
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if (offsetL < AUDIO_BLOCK_SAMPLES) {
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AudioOutputI2S_F32::block_left_offset = offsetL;
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} else {
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AudioOutputI2S_F32::block_left_offset = 0;
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AudioStream::release(blockL);
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AudioOutputI2S_F32::block_left_1st = AudioOutputI2S_F32::block_left_2nd;
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AudioOutputI2S_F32::block_left_2nd = NULL;
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}
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if (offsetR < AUDIO_BLOCK_SAMPLES) {
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AudioOutputI2S_F32::block_right_offset = offsetR;
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} else {
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AudioOutputI2S_F32::block_right_offset = 0;
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AudioStream::release(blockR);
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AudioOutputI2S_F32::block_right_1st = AudioOutputI2S_F32::block_right_2nd;
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AudioOutputI2S_F32::block_right_2nd = NULL;
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}
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#else
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const int16_t *src, *end;
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int16_t *dest;
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audio_block_t *block;
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uint32_t saddr, offset;
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saddr = (uint32_t)(dma.CFG->SAR);
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dma.clearInterrupt();
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if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
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// DMA is transmitting the first half of the buffer
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// so we must fill the second half
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dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
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end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
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if (AudioOutputI2S_F32::update_responsibility) AudioStream_F32::update_all();
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} else {
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// DMA is transmitting the second half of the buffer
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// so we must fill the first half
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dest = (int16_t *)i2s_tx_buffer;
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end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
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}
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block = AudioOutputI2S_F32::block_left_1st;
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if (block) {
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offset = AudioOutputI2S_F32::block_left_offset;
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src = &block->data[offset];
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do {
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*dest = *src++;
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dest += 2;
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} while (dest < end);
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offset += AUDIO_BLOCK_SAMPLES/2;
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if (offset < AUDIO_BLOCK_SAMPLES) {
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AudioOutputI2S_F32::block_left_offset = offset;
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} else {
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AudioOutputI2S_F32::block_left_offset = 0;
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AudioStream::release(block);
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AudioOutputI2S_F32::block_left_1st = AudioOutputI2S_F32::block_left_2nd;
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AudioOutputI2S_F32::block_left_2nd = NULL;
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}
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} else {
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do {
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*dest = 0;
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dest += 2;
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} while (dest < end);
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}
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dest -= AUDIO_BLOCK_SAMPLES - 1;
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block = AudioOutputI2S_F32::block_right_1st;
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if (block) {
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offset = AudioOutputI2S_F32::block_right_offset;
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src = &block->data[offset];
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do {
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*dest = *src++;
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dest += 2;
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} while (dest < end);
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offset += AUDIO_BLOCK_SAMPLES/2;
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if (offset < AUDIO_BLOCK_SAMPLES) {
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AudioOutputI2S_F32::block_right_offset = offset;
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} else {
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AudioOutputI2S_F32::block_right_offset = 0;
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AudioStream::release(block);
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AudioOutputI2S_F32::block_right_1st = AudioOutputI2S_F32::block_right_2nd;
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AudioOutputI2S_F32::block_right_2nd = NULL;
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}
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} else {
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do {
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*dest = 0;
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dest += 2;
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} while (dest < end);
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}
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#endif
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}
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void AudioOutputI2S_F32::update(void)
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{
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// null audio device: discard all incoming data
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//if (!active) return;
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//audio_block_t *block = receiveReadOnly();
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//if (block) release(block);
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audio_block_t *block;
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audio_block_f32_t *block_f32;
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block_f32 = receiveReadOnly_f32(0); // input 0 = left channel
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if (block_f32) {
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//convert F32 to Int16
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block = AudioStream::allocate();
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arm_float_to_q15((float32_t *)(block_f32->data),(q15_t *)(block->data), AUDIO_BLOCK_SAMPLES);
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AudioStream_F32::release(block_f32);
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//now process the data blocks
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__disable_irq();
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if (block_left_1st == NULL) {
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block_left_1st = block;
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block_left_offset = 0;
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__enable_irq();
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} else if (block_left_2nd == NULL) {
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block_left_2nd = block;
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__enable_irq();
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} else {
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audio_block_t *tmp = block_left_1st;
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block_left_1st = block_left_2nd;
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block_left_2nd = block;
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block_left_offset = 0;
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__enable_irq();
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AudioStream::release(tmp);
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}
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}
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block_f32 = receiveReadOnly_f32(1); // input 1 = right channel
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if (block_f32) {
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//convert F32 to Int16
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block = AudioStream::allocate();
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arm_float_to_q15((float32_t *)(block_f32->data),(q15_t *)(block->data), AUDIO_BLOCK_SAMPLES);
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AudioStream_F32::release(block_f32);
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__disable_irq();
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if (block_right_1st == NULL) {
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block_right_1st = block;
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block_right_offset = 0;
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__enable_irq();
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} else if (block_right_2nd == NULL) {
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block_right_2nd = block;
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__enable_irq();
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} else {
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audio_block_t *tmp = block_right_1st;
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block_right_1st = block_right_2nd;
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block_right_2nd = block;
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block_right_offset = 0;
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__enable_irq();
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AudioStream::release(tmp);
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}
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}
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}
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// MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
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//
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#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
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// PLL is at 96 MHz in these modes
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#define MCLK_MULT 2
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#define MCLK_DIV 17
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#elif F_CPU == 72000000
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#define MCLK_MULT 8
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#define MCLK_DIV 51
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#elif F_CPU == 120000000
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#define MCLK_MULT 8
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#define MCLK_DIV 85
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#elif F_CPU == 144000000
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#define MCLK_MULT 4
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#define MCLK_DIV 51
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#elif F_CPU == 168000000
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#define MCLK_MULT 8
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#define MCLK_DIV 119
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#elif F_CPU == 180000000
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#define MCLK_MULT 16
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#define MCLK_DIV 255
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#define MCLK_SRC 0
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#elif F_CPU == 192000000
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#define MCLK_MULT 1
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#define MCLK_DIV 17
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#elif F_CPU == 216000000
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#define MCLK_MULT 8
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#define MCLK_DIV 153
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#define MCLK_SRC 0
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#elif F_CPU == 240000000
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#define MCLK_MULT 4
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#define MCLK_DIV 85
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#elif F_CPU == 16000000
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#define MCLK_MULT 12
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#define MCLK_DIV 17
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#else
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#error "This CPU Clock Speed is not supported by the Audio library";
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#endif
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#ifndef MCLK_SRC
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#if F_CPU >= 20000000
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#define MCLK_SRC 3 // the PLL
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#else
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#define MCLK_SRC 0 // system clock
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#endif
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#endif
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void AudioOutputI2S_F32::config_i2s(void)
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{
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SIM_SCGC6 |= SIM_SCGC6_I2S;
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SIM_SCGC7 |= SIM_SCGC7_DMA;
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
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// if either transmitter or receiver is enabled, do nothing
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if (I2S0_TCSR & I2S_TCSR_TE) return;
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if (I2S0_RCSR & I2S_RCSR_RE) return;
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// enable MCLK output
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I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
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while (I2S0_MCR & I2S_MCR_DUF) ;
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I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
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// configure transmitter
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I2S0_TMR = 0;
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I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
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I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
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| I2S_TCR2_BCD | I2S_TCR2_DIV(3);
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I2S0_TCR3 = I2S_TCR3_TCE;
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I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
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| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
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I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
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// configure receiver (sync'd to transmitter clocks)
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I2S0_RMR = 0;
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I2S0_RCR1 = I2S_RCR1_RFW(1);
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I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
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| I2S_RCR2_BCD | I2S_RCR2_DIV(3);
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I2S0_RCR3 = I2S_RCR3_RCE;
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I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
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| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
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I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
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// configure pin mux for 3 clock signals
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
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}
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/******************************************************************/
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/*
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void AudioOutputI2Sslave::begin(void)
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{
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dma.begin(true); // Allocate the DMA channel first
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//pinMode(2, OUTPUT);
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block_left_1st = NULL;
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block_right_1st = NULL;
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AudioOutputI2Sslave::config_i2s();
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
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#if defined(KINETISK)
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dma.TCD->SADDR = i2s_tx_buffer;
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dma.TCD->SOFF = 2;
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
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dma.TCD->NBYTES_MLNO = 2;
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dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
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dma.TCD->DADDR = &I2S0_TDR0;
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dma.TCD->DOFF = 0;
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dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
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dma.TCD->DLASTSGA = 0;
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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
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#endif
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
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update_responsibility = update_setup();
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dma.enable();
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I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE | I2S_TCSR_FR;
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dma.attachInterrupt(isr);
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}
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void AudioOutputI2Sslave::config_i2s(void)
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{
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SIM_SCGC6 |= SIM_SCGC6_I2S;
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SIM_SCGC7 |= SIM_SCGC7_DMA;
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SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
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// if either transmitter or receiver is enabled, do nothing
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if (I2S0_TCSR & I2S_TCSR_TE) return;
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if (I2S0_RCSR & I2S_RCSR_RE) return;
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// Select input clock 0
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// Configure to input the bit-clock from pin, bypasses the MCLK divider
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I2S0_MCR = I2S_MCR_MICS(0);
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I2S0_MDR = 0;
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// configure transmitter
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I2S0_TMR = 0;
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I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
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I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;
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I2S0_TCR3 = I2S_TCR3_TCE;
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I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(15) | I2S_TCR4_MF
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| I2S_TCR4_FSE | I2S_TCR4_FSP;
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I2S0_TCR5 = I2S_TCR5_WNW(15) | I2S_TCR5_W0W(15) | I2S_TCR5_FBT(15);
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// configure receiver (sync'd to transmitter clocks)
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I2S0_RMR = 0;
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I2S0_RCR1 = I2S_RCR1_RFW(1);
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I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;
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I2S0_RCR3 = I2S_RCR3_RCE;
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I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(15) | I2S_RCR4_MF
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| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
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I2S0_RCR5 = I2S_RCR5_WNW(15) | I2S_RCR5_W0W(15) | I2S_RCR5_FBT(15);
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// configure pin mux for 3 clock signals
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CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
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CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
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CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
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}
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*/ |