boblark
4 years ago
parent
0af24d2bef
commit
4fb7a512ab
@ -0,0 +1,72 @@ |
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#include <Audio.h> |
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#include <OpenAudio_ArduinoLibrary.h> |
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#define USE_F32_IO 1 |
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AudioControlSGTL5000 sgtl5000_1; |
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#if USE_F32_IO |
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#if USE_CODEC_IN |
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#else // Use Sine Input
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AudioSynthWaveformSine_F32 sine1; |
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AudioConvert_F32toI16 float2Int1; //, float2Int2;
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AudioOutputI2S i2sOut; |
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//AudioOutputI2S_OA_F32 i2sOut;
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/*
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//Make all of the audio connections
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AudioConnection patchCord1(i2s_in, 0, int2Float1, 0); |
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AudioConnection patchCord2(i2s_in, 1, int2Float2, 0); |
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AudioConnection_F32 patchCord10(int2Float1, 0, gain1, 0); |
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AudioConnection_F32 patchCord11(int2Float2, 0, gain2, 0); |
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* */ |
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AudioConnection_F32 pc1(sine1, 0, float2Int1, 0); |
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AudioConnection_F32 patchCord12(float2Int1, 0, i2sOut, 0);
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//AudioConnection_F32 patchCord13(gain2, 0, float2Int2, 0);
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//AudioConnection_F32 patchCord20(sine1, 0, i2sOut, 0);
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//AudioConnection_F32 patchCord21(sine1, 0, i2sOut, 1);
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//AudioConnection_F32 patchCord12(gain1, 0, i2sOut, 0);
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//AudioConnection_F32 patchCord13(gain2, 0, i2sOut, 1);
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/*AudioInputI2S i2s_in;
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AudioConvert_I16toF32 int2Float1, int2Float2; |
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AudioEffectGain_F32 gain1, gain2; |
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* */ |
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void setup(void) { |
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Serial.begin(1); delay(1000); |
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Serial.println("Open Audio Test Input and Output");
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AudioMemory(10); |
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AudioMemory_F32(10); |
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sgtl5000_1.enable(); |
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sgtl5000_1.inputSelect(AUDIO_INPUT_LINEIN); |
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sine1.frequency(300.0); |
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sine1.amplitude(0.01f); |
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sine1.begin(); |
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/*
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//sgtl5000_1.adcHighPassFilterEnable(); //LOW OUTPUT NO WHINEY NOISE, gain has no effect---Direct path??
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//reduces noise. https://forum.pjrc.com/threads/27215-24-bit-audio-boards?p=78831&viewfull=1#post78831
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sgtl5000_1.adcHighPassFilterDisable(); gain1.setGain_dB(40); // NOISE WITH WHINEY PITCH
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gain2.setGain_dB(40);
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*/ |
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}
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void loop() { |
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} |
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@ -0,0 +1,11 @@ |
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/* TestLoader.ino Bob Larkin 3 July 2020
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*/ |
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void setup(void) { |
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Serial.begin(9600); |
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while(!Serial) ; |
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Serial.println("Test Loader"); |
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} |
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void loop() { |
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} |
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@ -0,0 +1,20 @@ |
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#include <Audio.h> |
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AudioSynthWaveformSine sine1; |
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AudioOutputI2S i2sOut; |
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AudioConnection patchCord1(sine1, 0, i2sOut, 0); |
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AudioConnection patchCord2(sine1, 0, i2sOut, 1); |
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AudioControlSGTL5000 sgtl5000_1; |
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void setup(void) { |
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Serial.begin(1); delay(1000); |
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Serial.println("Teensy Audio, Test Loader");
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AudioMemory(10); |
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sgtl5000_1.enable(); |
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sine1.frequency(300.0); |
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sine1.amplitude(0.005f); |
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}
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void loop() { |
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} |
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@ -0,0 +1,77 @@ |
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/* TestOutput_float.ino Bob Larkin 3 July 2020
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*
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* Test for #define USE_F32_IO either 0 or 1, all OK on T3.6 |
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*
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*/ |
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#include <Audio.h> |
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#include <OpenAudio_ArduinoLibrary.h> |
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// NOT WORKING for USE_F32_IO 1 <<<<<<<<<<<<<<<
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#define ALL_TEENSY_AUDIO 0 |
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#define USE_F32_IO 1 |
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#if ALL_TEENSY_AUDIO |
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AudioSynthWaveformSine sine1; |
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AudioOutputI2S i2sOut; |
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AudioConnection patchCord1(sine1, 0, i2sOut, 0); |
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AudioConnection patchCord2(sine1, 0, i2sOut, 1); |
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AudioControlSGTL5000 sgtl5000_1; |
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void setup(void) { |
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Serial.begin(1); delay(1000); |
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Serial.println("Teensy Audio, No F32");
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AudioMemory(10); |
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sgtl5000_1.enable(); |
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sine1.frequency(300.0); |
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sine1.amplitude(0.005f); |
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}
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void loop() { |
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} |
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// ================================================
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#else // OpenAudio F32
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#if USE_F32_IO |
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AudioSynthWaveformSine_F32 sine1; |
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AudioOutputI2S_OA_F32 i2sOut; |
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AudioConnection_F32 patchCord1(sine1, 0, i2sOut, 0); |
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AudioConnection_F32 patchCord2(sine1, 0, i2sOut, 1); |
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#else // Use F32toI16 convert and I16 out
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AudioSynthWaveformSine_F32 sine1; |
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AudioConvert_F32toI16 float2Int1, float2Int2; |
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AudioOutputI2S i2sOut; |
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AudioConnection_F32 patchCord5(sine1, 0, float2Int1, 0); |
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AudioConnection_F32 patchCord6(sine1, 0, float2Int2, 0); |
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AudioConnection patchCord7(float2Int1, 0, i2sOut, 0); |
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AudioConnection patchCord8(float2Int2, 0, i2sOut, 1); |
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#endif |
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AudioControlSGTL5000 sgtl5000_1; |
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void setup(void) { |
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Serial.begin(1); delay(1000); |
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#if USE_F32_IO |
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Serial.println("Open Audio: Test direct F32 Output");
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#else |
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Serial.println("Open Audio: Test Convert to Teensy Audio I16 Output"); |
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#endif |
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AudioMemory(10); |
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AudioMemory_F32(10); |
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//delay(1); Serial.println("Start i2s_f32 out");
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//i2sOut.begin();
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//delay(1); Serial.println("Start codec");
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sgtl5000_1.enable(); |
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sine1.frequency(300.0); |
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sine1.amplitude(0.005f); |
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sine1.begin(); |
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}
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void loop() { |
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} |
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#endif // ALL_TEENSY_AUDIO
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@ -0,0 +1,46 @@ |
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/* Teensyduino Audio Memcpy
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* Copyright (c) 2016 Frank Bösing |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining |
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* a copy of this software and associated documentation files (the |
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* "Software"), to deal in the Software without restriction, including |
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* without limitation the rights to use, copy, modify, merge, publish, |
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* distribute, sublicense, and/or sell copies of the Software, and to |
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* permit persons to whom the Software is furnished to do so, subject to |
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* the following conditions: |
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* |
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* 1. The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* 2. If the Software is incorporated into a build system that allows |
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* selection among a list of target devices, then similar target |
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* devices manufactured by PJRC.COM must be included in the list of |
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* target devices and selectable in the same manner. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef memcpy_audio_h_ |
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#define memcpy_audio_h_ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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void memcpy_tointerleaveLR(int16_t *dst, const int16_t *srcL, const int16_t *srcR); |
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void memcpy_tointerleaveL(int16_t *dst, const int16_t *srcL); |
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void memcpy_tointerleaveR(int16_t *dst, const int16_t *srcR); |
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void memcpy_tointerleaveQuad(int16_t *dst, const int16_t *src1, const int16_t *src2, |
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const int16_t *src3, const int16_t *src4); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif |
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@ -0,0 +1,581 @@ |
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/* output_i2s_OA_f32.cpp |
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* |
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* This is Teensy Audio output_i2s.h altered to support OpenAudio float (F32) |
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* to allow direct output of F32 blocks to the codec. It is the Teensy Audio output |
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* class with a conversion of float to int16 at the beginning. Bob Larkin |
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* June 2020 |
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* |
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* Additions under MIT license, and all the original is: |
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* Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com |
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* |
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* Development of this audio library was funded by PJRC.COM, LLC by sales of |
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* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop |
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* open source software by purchasing Teensy or other PJRC products. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice, development funding notice, and this permission |
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* notice shall be included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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#include <Arduino.h> |
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#include "output_i2s_OA_f32.h" |
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#include "memcpy_audio.h" |
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audio_block_t * AudioOutputI2S_OA_F32::block_left_1st = NULL; |
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audio_block_t * AudioOutputI2S_OA_F32::block_right_1st = NULL; |
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audio_block_t * AudioOutputI2S_OA_F32::block_left_2nd = NULL; |
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audio_block_t * AudioOutputI2S_OA_F32::block_right_2nd = NULL; |
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uint16_t AudioOutputI2S_OA_F32::block_left_offset = 0; |
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uint16_t AudioOutputI2S_OA_F32::block_right_offset = 0; |
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bool AudioOutputI2S_OA_F32::update_responsibility = false; |
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DMAChannel AudioOutputI2S_OA_F32::dma(false); |
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DMAMEM __attribute__((aligned(32))) static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; |
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#if defined(__IMXRT1062__) |
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#include "utility/imxrt_hw.h" |
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#endif |
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void AudioOutputI2S_OA_F32::begin(void) |
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{ |
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dma.begin(true); // Allocate the DMA channel first |
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block_left_1st = NULL; |
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block_right_1st = NULL; |
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config_i2s(); |
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#if defined(KINETISK) |
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CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 |
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dma.TCD->SADDR = i2s_tx_buffer; |
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dma.TCD->SOFF = 2; |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->NBYTES_MLNO = 2; |
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dma.TCD->SLAST = -sizeof(i2s_tx_buffer); |
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dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2); |
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dma.TCD->DOFF = 0; |
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dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->DLASTSGA = 0; |
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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
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dma.enable(); |
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I2S0_TCSR = I2S_TCSR_SR; |
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I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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#elif defined(__IMXRT1062__) |
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CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
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dma.TCD->SADDR = i2s_tx_buffer; |
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dma.TCD->SOFF = 2; |
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dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
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dma.TCD->NBYTES_MLNO = 2; |
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dma.TCD->SLAST = -sizeof(i2s_tx_buffer); |
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dma.TCD->DOFF = 0; |
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dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->DLASTSGA = 0; |
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dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
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dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
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dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); |
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dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); |
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dma.enable(); |
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I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; |
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I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
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#endif |
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update_responsibility = update_setup(); |
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dma.attachInterrupt(isr); |
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} // end begin() |
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void AudioOutputI2S_OA_F32::isr(void) |
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{ |
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#if defined(KINETISK) || defined(__IMXRT1062__) |
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int16_t *dest; |
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audio_block_t *blockL, *blockR; |
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uint32_t saddr, offsetL, offsetR; |
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saddr = (uint32_t)(dma.TCD->SADDR); |
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dma.clearInterrupt(); |
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if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { |
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// DMA is transmitting the first half of the buffer |
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// so we must fill the second half |
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dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; |
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if (AudioOutputI2S_OA_F32::update_responsibility) AudioStream_F32::update_all(); |
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} else { |
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// DMA is transmitting the second half of the buffer |
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// so we must fill the first half |
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dest = (int16_t *)i2s_tx_buffer; |
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} |
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blockL = AudioOutputI2S_OA_F32::block_left_1st; // These 2 are I16* |
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blockR = AudioOutputI2S_OA_F32::block_right_1st; |
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offsetL = AudioOutputI2S_OA_F32::block_left_offset; |
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offsetR = AudioOutputI2S_OA_F32::block_right_offset; |
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if (blockL && blockR) { |
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memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR); |
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offsetL += AUDIO_BLOCK_SAMPLES / 2; |
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offsetR += AUDIO_BLOCK_SAMPLES / 2; |
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} else if (blockL) { |
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memcpy_tointerleaveL(dest, blockL->data + offsetL); |
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offsetL += AUDIO_BLOCK_SAMPLES / 2; |
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} else if (blockR) { |
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memcpy_tointerleaveR(dest, blockR->data + offsetR); |
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offsetR += AUDIO_BLOCK_SAMPLES / 2; |
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} else { |
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memset(dest,0,AUDIO_BLOCK_SAMPLES * 2); |
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} |
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arm_dcache_flush_delete(dest, sizeof(i2s_tx_buffer) / 2 ); |
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if (offsetL < AUDIO_BLOCK_SAMPLES) { |
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AudioOutputI2S_OA_F32::block_left_offset = offsetL; |
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} else { |
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AudioOutputI2S_OA_F32::block_left_offset = 0; |
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AudioStream::release(blockL); |
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AudioOutputI2S_OA_F32::block_left_1st = AudioOutputI2S_OA_F32::block_left_2nd; |
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AudioOutputI2S_OA_F32::block_left_2nd = NULL; |
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} |
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if (offsetR < AUDIO_BLOCK_SAMPLES) { |
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AudioOutputI2S_OA_F32::block_right_offset = offsetR; |
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} else { |
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AudioOutputI2S_OA_F32::block_right_offset = 0; |
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AudioStream::release(blockR); |
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AudioOutputI2S_OA_F32::block_right_1st = AudioOutputI2S_OA_F32::block_right_2nd; |
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AudioOutputI2S_OA_F32::block_right_2nd = NULL; |
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} |
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#else |
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// This is T3.x, x<5. Those would not seem to be candidates for F32 audio processing? |
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const int16_t *src, *end; |
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int16_t *dest; |
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audio_block_t *block; |
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uint32_t saddr, offset; |
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saddr = (uint32_t)(dma.CFG->SAR); |
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dma.clearInterrupt(); |
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if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) { |
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// DMA is transmitting the first half of the buffer |
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// so we must fill the second half |
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dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; |
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end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES]; |
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if (AudioOutputI2S_OA_F32::update_responsibility) AudioStream::update_all(); |
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} else { |
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// DMA is transmitting the second half of the buffer |
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// so we must fill the first half |
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dest = (int16_t *)i2s_tx_buffer; |
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end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2]; |
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} |
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block = AudioOutputI2S_OA_F32::block_left_1st; |
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if (block) { |
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offset = AudioOutputI2S_OA_F32::block_left_offset; |
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src = &block->data[offset]; |
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do { |
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*dest = *src++; |
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dest += 2; |
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} while (dest < end); |
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offset += AUDIO_BLOCK_SAMPLES/2; |
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if (offset < AUDIO_BLOCK_SAMPLES) { |
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AudioOutputI2S_OA_F32::block_left_offset = offset; |
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} else { |
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AudioOutputI2S_OA_F32::block_left_offset = 0; |
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AudioStream::release(block); |
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AudioOutputI2S_OA_F32::block_left_1st = AudioOutputI2S_OA_F32::block_left_2nd; |
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AudioOutputI2S_OA_F32::block_left_2nd = NULL; |
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} |
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} else { |
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do { |
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*dest = 0; |
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dest += 2; |
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} while (dest < end); |
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} |
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dest -= AUDIO_BLOCK_SAMPLES - 1; |
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block = AudioOutputI2S_OA_F32::block_right_1st; |
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if (block) { |
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offset = AudioOutputI2S_OA_F32::block_right_offset; |
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src = &block->data[offset]; |
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do { |
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*dest = *src++; |
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dest += 2; |
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} while (dest < end); |
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offset += AUDIO_BLOCK_SAMPLES/2; |
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if (offset < AUDIO_BLOCK_SAMPLES) { |
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AudioOutputI2S_OA_F32::block_right_offset = offset; |
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} else { |
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AudioOutputI2S_OA_F32::block_right_offset = 0; |
||||
AudioStream::release(block); |
||||
AudioOutputI2S_OA_F32::block_right_1st = AudioOutputI2S_OA_F32::block_right_2nd; |
||||
AudioOutputI2S_OA_F32::block_right_2nd = NULL; |
||||
} |
||||
} else { |
||||
do { |
||||
*dest = 0; |
||||
dest += 2; |
||||
} while (dest < end); |
||||
} |
||||
#endif |
||||
} |
||||
|
||||
void AudioOutputI2S_OA_F32::update(void) |
||||
{ |
||||
audio_block_f32_t *blockF32; |
||||
audio_block_t *blockI16; |
||||
|
||||
blockF32 = AudioStream_F32::receiveReadOnly_f32(0); // input 0 = left |
||||
blockI16 = AudioStream::allocate(); |
||||
if (blockF32) { |
||||
// Change F32 to I16 |
||||
for(int i=0; i<128; i++) { |
||||
blockI16->data[i] = (int16_t)(32768.0f*blockF32->data[i]); |
||||
} |
||||
AudioStream_F32::release(blockF32); // End of F32 activity |
||||
|
||||
// From here down to end of left channel is the same as for I16 Teensy Audio |
||||
// Now I16, so sort out the DMA data |
||||
__disable_irq(); |
||||
if (block_left_1st == NULL) { |
||||
block_left_1st = blockI16; |
||||
block_left_offset = 0; |
||||
__enable_irq(); |
||||
} else if (block_left_2nd == NULL) { |
||||
block_left_2nd = blockI16; |
||||
__enable_irq(); |
||||
} else { |
||||
audio_block_t *tmp = block_left_1st; |
||||
block_left_1st = block_left_2nd; |
||||
block_left_2nd = blockI16; |
||||
block_left_offset = 0; |
||||
__enable_irq(); |
||||
AudioStream::release(tmp); |
||||
} |
||||
} |
||||
|
||||
blockF32 = AudioStream_F32::receiveReadOnly_f32(1); // input 1 = right |
||||
if (blockF32) { |
||||
for(int i=0; i<128; i++) { |
||||
blockI16->data[i] = (int16_t)(32768.0f*blockF32->data[i]); |
||||
} |
||||
AudioStream_F32::release(blockF32); // Second end of F32 activity |
||||
|
||||
__disable_irq(); |
||||
if (block_right_1st == NULL) { |
||||
block_right_1st = blockI16; |
||||
block_right_offset = 0; |
||||
__enable_irq(); |
||||
} else if (block_right_2nd == NULL) { |
||||
block_right_2nd = blockI16; |
||||
__enable_irq(); |
||||
} else { |
||||
audio_block_t *tmp = block_right_1st; |
||||
block_right_1st = block_right_2nd; |
||||
block_right_2nd = blockI16; |
||||
block_right_offset = 0; |
||||
__enable_irq(); |
||||
AudioStream::release(tmp); |
||||
} |
||||
} |
||||
AudioStream::release(blockI16); |
||||
} // end update() |
||||
|
||||
#if defined(KINETISK) || defined(KINETISL) |
||||
// MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate |
||||
// |
||||
#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000 |
||||
// PLL is at 96 MHz in these modes |
||||
#define MCLK_MULT 2 |
||||
#define MCLK_DIV 17 |
||||
#elif F_CPU == 72000000 |
||||
#define MCLK_MULT 8 |
||||
#define MCLK_DIV 51 |
||||
#elif F_CPU == 120000000 |
||||
#define MCLK_MULT 8 |
||||
#define MCLK_DIV 85 |
||||
#elif F_CPU == 144000000 |
||||
#define MCLK_MULT 4 |
||||
#define MCLK_DIV 51 |
||||
#elif F_CPU == 168000000 |
||||
#define MCLK_MULT 8 |
||||
#define MCLK_DIV 119 |
||||
#elif F_CPU == 180000000 |
||||
#define MCLK_MULT 16 |
||||
#define MCLK_DIV 255 |
||||
#define MCLK_SRC 0 |
||||
#elif F_CPU == 192000000 |
||||
#define MCLK_MULT 1 |
||||
#define MCLK_DIV 17 |
||||
#elif F_CPU == 216000000 |
||||
#define MCLK_MULT 12 |
||||
#define MCLK_DIV 17 |
||||
#define MCLK_SRC 1 |
||||
#elif F_CPU == 240000000 |
||||
#define MCLK_MULT 2 |
||||
#define MCLK_DIV 85 |
||||
#define MCLK_SRC 0 |
||||
#elif F_CPU == 256000000 |
||||
#define MCLK_MULT 12 |
||||
#define MCLK_DIV 17 |
||||
#define MCLK_SRC 1 |
||||
#elif F_CPU == 16000000 |
||||
#define MCLK_MULT 12 |
||||
#define MCLK_DIV 17 |
||||
#else |
||||
#error "This CPU Clock Speed is not supported by the Audio library"; |
||||
#endif |
||||
|
||||
#ifndef MCLK_SRC |
||||
#if F_CPU >= 20000000 |
||||
#define MCLK_SRC 3 // the PLL |
||||
#else |
||||
#define MCLK_SRC 0 // system clock |
||||
#endif |
||||
#endif |
||||
#endif |
||||
|
||||
void AudioOutputI2S_OA_F32::config_i2s(void) |
||||
{ |
||||
#if defined(KINETISK) || defined(KINETISL) |
||||
SIM_SCGC6 |= SIM_SCGC6_I2S; |
||||
SIM_SCGC7 |= SIM_SCGC7_DMA; |
||||
SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
||||
|
||||
// if either transmitter or receiver is enabled, do nothing |
||||
if (I2S0_TCSR & I2S_TCSR_TE) return; |
||||
if (I2S0_RCSR & I2S_RCSR_RE) return; |
||||
|
||||
// enable MCLK output |
||||
I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE; |
||||
while (I2S0_MCR & I2S_MCR_DUF) ; |
||||
I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1)); |
||||
|
||||
// configure transmitter |
||||
I2S0_TMR = 0; |
||||
I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size |
||||
I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1) |
||||
| I2S_TCR2_BCD | I2S_TCR2_DIV(1); |
||||
I2S0_TCR3 = I2S_TCR3_TCE; |
||||
I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF |
||||
| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD; |
||||
I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); |
||||
|
||||
// configure receiver (sync'd to transmitter clocks) |
||||
I2S0_RMR = 0; |
||||
I2S0_RCR1 = I2S_RCR1_RFW(1); |
||||
I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1) |
||||
| I2S_RCR2_BCD | I2S_RCR2_DIV(1); |
||||
I2S0_RCR3 = I2S_RCR3_RCE; |
||||
I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF |
||||
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; |
||||
I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); |
||||
|
||||
// configure pin mux for 3 clock signals |
||||
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
||||
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
||||
CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
||||
|
||||
#elif defined(__IMXRT1062__) |
||||
|
||||
CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); |
||||
|
||||
// if either transmitter or receiver is enabled, do nothing |
||||
if (I2S1_TCSR & I2S_TCSR_TE) return; |
||||
if (I2S1_RCSR & I2S_RCSR_RE) return; |
||||
//PLL: |
||||
int fs = AUDIO_SAMPLE_RATE_EXACT; |
||||
// PLL between 27*24 = 648MHz und 54*24=1296MHz |
||||
int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4 |
||||
int n2 = 1 + (24000000 * 27) / (fs * 256 * n1); |
||||
|
||||
double C = ((double)fs * 256 * n1 * n2) / 24000000; |
||||
int c0 = C; |
||||
int c2 = 10000; |
||||
int c1 = C * c2 - (c0 * c2); |
||||
set_audioClock(c0, c1, c2); |
||||
|
||||
// clear SAI1_CLK register locations |
||||
CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK)) |
||||
| CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4 |
||||
CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK)) |
||||
| CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07 |
||||
| CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f |
||||
|
||||
// Select MCLK |
||||
IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 |
||||
& ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)) |
||||
| (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0)); |
||||
|
||||
CORE_PIN23_CONFIG = 3; //1:MCLK |
||||
CORE_PIN21_CONFIG = 3; //1:RX_BCLK |
||||
CORE_PIN20_CONFIG = 3; //1:RX_SYNC |
||||
|
||||
int rsync = 0; |
||||
int tsync = 1; |
||||
|
||||
I2S1_TMR = 0; |
||||
//I2S1_TCSR = (1<<25); //Reset |
||||
I2S1_TCR1 = I2S_TCR1_RFW(1); |
||||
I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async; |
||||
| (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1)); |
||||
I2S1_TCR3 = I2S_TCR3_TCE; |
||||
I2S1_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF |
||||
| I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP; |
||||
I2S1_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1)); |
||||
|
||||
I2S1_RMR = 0; |
||||
//I2S1_RCSR = (1<<25); //Reset |
||||
I2S1_RCR1 = I2S_RCR1_RFW(1); |
||||
I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP // sync=0; rx is async; |
||||
| (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1)); |
||||
I2S1_RCR3 = I2S_RCR3_RCE; |
||||
I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF |
||||
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; |
||||
I2S1_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1)); |
||||
|
||||
#endif |
||||
} |
||||
|
||||
|
||||
/******************************************************************/ |
||||
|
||||
void AudioOutputI2Sslave_OA_F32::begin(void) |
||||
{ |
||||
|
||||
dma.begin(true); // Allocate the DMA channel first |
||||
|
||||
block_left_1st = NULL; |
||||
block_right_1st = NULL; |
||||
|
||||
AudioOutputI2Sslave_OA_F32::config_i2s(); |
||||
|
||||
#if defined(KINETISK) |
||||
CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0 |
||||
dma.TCD->SADDR = i2s_tx_buffer; |
||||
dma.TCD->SOFF = 2; |
||||
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
||||
dma.TCD->NBYTES_MLNO = 2; |
||||
dma.TCD->SLAST = -sizeof(i2s_tx_buffer); |
||||
dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2); |
||||
dma.TCD->DOFF = 0; |
||||
dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
||||
dma.TCD->DLASTSGA = 0; |
||||
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
||||
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
||||
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX); |
||||
dma.enable(); |
||||
|
||||
I2S0_TCSR = I2S_TCSR_SR; |
||||
I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
||||
|
||||
#elif defined(__IMXRT1062__) |
||||
CORE_PIN7_CONFIG = 3; //1:TX_DATA0 |
||||
dma.TCD->SADDR = i2s_tx_buffer; |
||||
dma.TCD->SOFF = 2; |
||||
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1); |
||||
dma.TCD->NBYTES_MLNO = 2; |
||||
dma.TCD->SLAST = -sizeof(i2s_tx_buffer); |
||||
dma.TCD->DOFF = 0; |
||||
dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
||||
dma.TCD->DLASTSGA = 0; |
||||
dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2; |
||||
dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2); |
||||
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR; |
||||
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX); |
||||
dma.enable(); |
||||
|
||||
I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE; |
||||
I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE; |
||||
#endif |
||||
|
||||
update_responsibility = update_setup(); |
||||
dma.attachInterrupt(isr); |
||||
} |
||||
|
||||
void AudioOutputI2Sslave_OA_F32::config_i2s(void) |
||||
{ |
||||
#if defined(KINETISK) |
||||
SIM_SCGC6 |= SIM_SCGC6_I2S; |
||||
SIM_SCGC7 |= SIM_SCGC7_DMA; |
||||
SIM_SCGC6 |= SIM_SCGC6_DMAMUX; |
||||
|
||||
// if either transmitter or receiver is enabled, do nothing |
||||
if (I2S0_TCSR & I2S_TCSR_TE) return; |
||||
if (I2S0_RCSR & I2S_RCSR_RE) return; |
||||
|
||||
// Select input clock 0 |
||||
// Configure to input the bit-clock from pin, bypasses the MCLK divider |
||||
I2S0_MCR = I2S_MCR_MICS(0); |
||||
I2S0_MDR = 0; |
||||
|
||||
// configure transmitter |
||||
I2S0_TMR = 0; |
||||
I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size |
||||
I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP; |
||||
|
||||
I2S0_TCR3 = I2S_TCR3_TCE; |
||||
I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF |
||||
| I2S_TCR4_FSE | I2S_TCR4_FSP; |
||||
|
||||
I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); |
||||
|
||||
// configure receiver (sync'd to transmitter clocks) |
||||
I2S0_RMR = 0; |
||||
I2S0_RCR1 = I2S_RCR1_RFW(1); |
||||
I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP; |
||||
|
||||
I2S0_RCR3 = I2S_RCR3_RCE; |
||||
I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF |
||||
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD; |
||||
|
||||
I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); |
||||
|
||||
// configure pin mux for 3 clock signals |
||||
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK) |
||||
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK |
||||
CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK |
||||
|
||||
#elif defined(__IMXRT1062__) |
||||
|
||||
CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON); |
||||
|
||||
// if either transmitter or receiver is enabled, do nothing |
||||
if (I2S1_TCSR & I2S_TCSR_TE) return; |
||||
if (I2S1_RCSR & I2S_RCSR_RE) return; |
||||
|
||||
// not using MCLK in slave mode - hope that's ok? |
||||
//CORE_PIN23_CONFIG = 3; // AD_B1_09 ALT3=SAI1_MCLK |
||||
CORE_PIN21_CONFIG = 3; // AD_B1_11 ALT3=SAI1_RX_BCLK |
||||
CORE_PIN20_CONFIG = 3; // AD_B1_10 ALT3=SAI1_RX_SYNC |
||||
IOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 1; // 1=GPIO_AD_B1_11_ALT3, page 868 |
||||
IOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 1; // 1=GPIO_AD_B1_10_ALT3, page 872 |
||||
|
||||
// configure transmitter |
||||
I2S1_TMR = 0; |
||||
I2S1_TCR1 = I2S_TCR1_RFW(1); // watermark at half fifo size |
||||
I2S1_TCR2 = I2S_TCR2_SYNC(1) | I2S_TCR2_BCP; |
||||
I2S1_TCR3 = I2S_TCR3_TCE; |
||||
I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF |
||||
| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_RCR4_FSD; |
||||
I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31); |
||||
|
||||
// configure receiver |
||||
I2S1_RMR = 0; |
||||
I2S1_RCR1 = I2S_RCR1_RFW(1); |
||||
I2S1_RCR2 = I2S_RCR2_SYNC(0) | I2S_TCR2_BCP; |
||||
I2S1_RCR3 = I2S_RCR3_RCE; |
||||
I2S1_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF |
||||
| I2S_RCR4_FSE | I2S_RCR4_FSP; |
||||
I2S1_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31); |
||||
|
||||
#endif |
||||
} |
||||
@ -0,0 +1,111 @@ |
||||
/* output_i2s_OA_f32.h |
||||
* |
||||
* This is Teensy Audio output_i2s.h altered to support OpenAudio float (F32) |
||||
* to allow direct output of F32 blocks to the codec. It is the Teensy Audio output |
||||
* class with a conversion of float to int16 at the beginning. Bob Larkin |
||||
* June 2020 |
||||
* |
||||
* This is basic: 128 word blocks, 16-bit integer word to the codec. It |
||||
* needs to be revisited for variable word block. |
||||
* |
||||
* Tested: Using TestOutput_float.ino, Runs T3.6 and T4.0 w/o error. |
||||
* |
||||
* Additions under MIT license, and all the original is: |
||||
* Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com |
||||
* |
||||
* Development of this audio library was funded by PJRC.COM, LLC by sales of |
||||
* Teensy and Audio Adaptor boards. Please support PJRC's efforts to develop |
||||
* open source software by purchasing Teensy or other PJRC products. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy |
||||
* of this software and associated documentation files (the "Software"), to deal |
||||
* in the Software without restriction, including without limitation the rights |
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
||||
* copies of the Software, and to permit persons to whom the Software is |
||||
* furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice, development funding notice, and this permission |
||||
* notice shall be included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
||||
* THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef output_i2s_OA_F32_h_ |
||||
#define output_i2s_OA_F32_h_ |
||||
|
||||
#include "Arduino.h" |
||||
#include "AudioStream.h" |
||||
#include "AudioStream_F32.h" |
||||
#include "DMAChannel.h" |
||||
|
||||
class AudioOutputI2S_OA_F32 : public AudioStream_F32 |
||||
{ |
||||
//GUI: inputs:2, outputs:0 //this line used for automatic generation of GUI node |
||||
public: |
||||
AudioOutputI2S_OA_F32(void) : AudioStream_F32(2, inputQueueArray) { |
||||
// Add 2 delays as experimental fix for possible Teensy Loader issue. |
||||
uint32_t ii; |
||||
uint32_t xx = 0; |
||||
for (ii=0; ii<1000; ii++) xx += ii; |
||||
begin(); |
||||
for (ii=0; ii<1000; ii++) xx += ii; |
||||
} |
||||
|
||||
/* This long form needs to be added <<<<<<<<<<<<<<<< |
||||
AudioOutputI2S_OA_F32(const AudioSettings_F32 &settings) : AudioStream_F32(2, inputQueueArray) |
||||
{ |
||||
sample_rate_Hz = settings.sample_rate_Hz; |
||||
audio_block_samples = settings.audio_block_samples; |
||||
begin(); |
||||
} |
||||
*/ |
||||
|
||||
virtual void update(void); |
||||
void begin(void); |
||||
friend class AudioInputI2S_OA_F32; |
||||
|
||||
/* These are 4, 6, and 8 channel options in I16 T4, not yet supported in F32 |
||||
#if defined(__IMXRT1062__) |
||||
friend class AudioOutputI2SQuad; |
||||
friend class AudioInputI2SQuad; |
||||
friend class AudioOutputI2SHex; |
||||
friend class AudioInputI2SHex; |
||||
friend class AudioOutputI2SOct; |
||||
friend class AudioInputI2SOct; |
||||
#endif |
||||
*/ |
||||
protected: |
||||
// Next fcn to be used only inside AudioOutputI2S_OA_F32slave !! |
||||
AudioOutputI2S_OA_F32(int dummy): AudioStream_F32(2, inputQueueArray) {} |
||||
static void config_i2s(void); |
||||
static audio_block_t *block_left_1st; |
||||
static audio_block_t *block_right_1st; |
||||
static bool update_responsibility; |
||||
static DMAChannel dma; |
||||
static void isr(void); |
||||
private: |
||||
static audio_block_t *block_left_2nd; |
||||
static audio_block_t *block_right_2nd; |
||||
static uint16_t block_left_offset; |
||||
static uint16_t block_right_offset; |
||||
audio_block_f32_t *inputQueueArray[2]; |
||||
}; |
||||
|
||||
class AudioOutputI2Sslave_OA_F32 : public AudioOutputI2S_OA_F32 |
||||
{ |
||||
public: |
||||
AudioOutputI2Sslave_OA_F32(void) : AudioOutputI2S_OA_F32(0) { begin(); } ; |
||||
void begin(void); |
||||
friend class AudioInputI2Sslave_OA_F32; |
||||
friend void dma_ch0_isr(void); |
||||
protected: |
||||
static void config_i2s(void); |
||||
}; |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue