OpenAudio_ArduinoLibrary/output_i2s_OA_F32.cpp.xxx

/* output_i2s_OA_f32.cpp
 * 
 * This is Teensy Audio output_i2s.h altered to support OpenAudio float (F32)
 * to allow direct output of F32 blocks to the codec. It is the Teensy Audio output
 * class with a conversion of float to int16 at the beginning.   Bob Larkin
 * June 2020
 * 
 * Additions under MIT license, and all the original is:
 * Copyright (c) 2014, Paul Stoffregen, paul@pjrc.com
 *
 * Development of this audio library was funded by PJRC.COM, LLC by sales of
 * Teensy and Audio Adaptor boards.  Please support PJRC's efforts to develop
 * open source software by purchasing Teensy or other PJRC products.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice, development funding notice, and this permission
 * notice shall be included in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <Arduino.h>
#include "output_i2s_OA_f32.h"
#include "memcpy_audio.h"

audio_block_t * AudioOutputI2S_OA_F32::block_left_1st = NULL;
audio_block_t * AudioOutputI2S_OA_F32::block_right_1st = NULL;
audio_block_t * AudioOutputI2S_OA_F32::block_left_2nd = NULL;
audio_block_t * AudioOutputI2S_OA_F32::block_right_2nd = NULL;
uint16_t  AudioOutputI2S_OA_F32::block_left_offset = 0;
uint16_t  AudioOutputI2S_OA_F32::block_right_offset = 0;
bool AudioOutputI2S_OA_F32::update_responsibility = false;
DMAChannel AudioOutputI2S_OA_F32::dma(false);
DMAMEM __attribute__((aligned(32))) static uint32_t i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];

#if defined(__IMXRT1062__)
#include "utility/imxrt_hw.h"
#endif

void AudioOutputI2S_OA_F32::begin(void)
{
    dma.begin(true); // Allocate the DMA channel first
    block_left_1st = NULL;
    block_right_1st = NULL;
    config_i2s();

#if defined(KINETISK)
    CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0

    dma.TCD->SADDR = i2s_tx_buffer;
    dma.TCD->SOFF = 2;
    dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
    dma.TCD->NBYTES_MLNO = 2;
    dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
    dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
    dma.TCD->DOFF = 0;
    dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->DLASTSGA = 0;
    dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
    dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
    dma.enable();

    I2S0_TCSR = I2S_TCSR_SR;
    I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;

#elif defined(__IMXRT1062__)
    CORE_PIN7_CONFIG  = 3;  //1:TX_DATA0
    dma.TCD->SADDR = i2s_tx_buffer;
    dma.TCD->SOFF = 2;
    dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
    dma.TCD->NBYTES_MLNO = 2;
    dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
    dma.TCD->DOFF = 0;
    dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->DLASTSGA = 0;
    dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
    dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2);
    dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
    dma.enable();

    I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
    I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
#endif
    update_responsibility = update_setup();
    dma.attachInterrupt(isr);
}    // end begin()

void AudioOutputI2S_OA_F32::isr(void)
{
#if defined(KINETISK) || defined(__IMXRT1062__)
    int16_t *dest;
    audio_block_t *blockL, *blockR;
    uint32_t saddr, offsetL, offsetR;

    saddr = (uint32_t)(dma.TCD->SADDR);
    dma.clearInterrupt();
    if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
        // DMA is transmitting the first half of the buffer
        // so we must fill the second half
        dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
        if (AudioOutputI2S_OA_F32::update_responsibility) AudioStream_F32::update_all();
    } else {
        // DMA is transmitting the second half of the buffer
        // so we must fill the first half
        dest = (int16_t *)i2s_tx_buffer;
    }

    blockL = AudioOutputI2S_OA_F32::block_left_1st;  // These 2 are I16*
    blockR = AudioOutputI2S_OA_F32::block_right_1st;
    offsetL = AudioOutputI2S_OA_F32::block_left_offset;
    offsetR = AudioOutputI2S_OA_F32::block_right_offset;

    if (blockL && blockR) {
        memcpy_tointerleaveLR(dest, blockL->data + offsetL, blockR->data + offsetR);
        offsetL += AUDIO_BLOCK_SAMPLES / 2;
        offsetR += AUDIO_BLOCK_SAMPLES / 2;
    } else if (blockL) {
        memcpy_tointerleaveL(dest, blockL->data + offsetL);
        offsetL += AUDIO_BLOCK_SAMPLES / 2;
    } else if (blockR) {
        memcpy_tointerleaveR(dest, blockR->data + offsetR);
        offsetR += AUDIO_BLOCK_SAMPLES / 2;
    } else {
        memset(dest,0,AUDIO_BLOCK_SAMPLES * 2);
    }

    arm_dcache_flush_delete(dest, sizeof(i2s_tx_buffer) / 2 );

    if (offsetL < AUDIO_BLOCK_SAMPLES) {
        AudioOutputI2S_OA_F32::block_left_offset = offsetL;
    } else {
        AudioOutputI2S_OA_F32::block_left_offset = 0;
        AudioStream::release(blockL);
        AudioOutputI2S_OA_F32::block_left_1st = AudioOutputI2S_OA_F32::block_left_2nd;
        AudioOutputI2S_OA_F32::block_left_2nd = NULL;
    }
    if (offsetR < AUDIO_BLOCK_SAMPLES) {
        AudioOutputI2S_OA_F32::block_right_offset = offsetR;
    } else {
        AudioOutputI2S_OA_F32::block_right_offset = 0;
        AudioStream::release(blockR);
        AudioOutputI2S_OA_F32::block_right_1st = AudioOutputI2S_OA_F32::block_right_2nd;
        AudioOutputI2S_OA_F32::block_right_2nd = NULL;
    }
#else
    // This is T3.x, x<5.  Those would not seem to be candidates for F32 audio processing?
    const int16_t *src, *end;
    int16_t *dest;
    audio_block_t *block;
    uint32_t saddr, offset;

    saddr = (uint32_t)(dma.CFG->SAR);
    dma.clearInterrupt();
    if (saddr < (uint32_t)i2s_tx_buffer + sizeof(i2s_tx_buffer) / 2) {
        // DMA is transmitting the first half of the buffer
        // so we must fill the second half
        dest = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
        end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES];
        if (AudioOutputI2S_OA_F32::update_responsibility) AudioStream::update_all();
    } else {
        // DMA is transmitting the second half of the buffer
        // so we must fill the first half
        dest = (int16_t *)i2s_tx_buffer;
        end = (int16_t *)&i2s_tx_buffer[AUDIO_BLOCK_SAMPLES/2];
    }

    block = AudioOutputI2S_OA_F32::block_left_1st;
    if (block) {
        offset = AudioOutputI2S_OA_F32::block_left_offset;
        src = &block->data[offset];
        do {
            *dest = *src++;
            dest += 2;
        } while (dest < end);
        offset += AUDIO_BLOCK_SAMPLES/2;
        if (offset < AUDIO_BLOCK_SAMPLES) {
            AudioOutputI2S_OA_F32::block_left_offset = offset;
        } else {
            AudioOutputI2S_OA_F32::block_left_offset = 0;
            AudioStream::release(block);
            AudioOutputI2S_OA_F32::block_left_1st = AudioOutputI2S_OA_F32::block_left_2nd;
            AudioOutputI2S_OA_F32::block_left_2nd = NULL;
        }
    } else {
        do {
            *dest = 0;
            dest += 2;
        } while (dest < end);
    }
    dest -= AUDIO_BLOCK_SAMPLES - 1;
    block = AudioOutputI2S_OA_F32::block_right_1st;
    if (block) {
        offset = AudioOutputI2S_OA_F32::block_right_offset;
        src = &block->data[offset];
        do {
            *dest = *src++;
            dest += 2;
        } while (dest < end);
        offset += AUDIO_BLOCK_SAMPLES/2;
        if (offset < AUDIO_BLOCK_SAMPLES) {
            AudioOutputI2S_OA_F32::block_right_offset = offset;
        } else {
            AudioOutputI2S_OA_F32::block_right_offset = 0;
            AudioStream::release(block);
            AudioOutputI2S_OA_F32::block_right_1st = AudioOutputI2S_OA_F32::block_right_2nd;
            AudioOutputI2S_OA_F32::block_right_2nd = NULL;
        }
    } else {
        do {
            *dest = 0;
            dest += 2;
        } while (dest < end);
    }
#endif
}

void AudioOutputI2S_OA_F32::update(void)
{
    audio_block_f32_t *blockF32;
    audio_block_t *blockI16;
    
    blockF32 = AudioStream_F32::receiveReadOnly_f32(0); // input 0 = left
    blockI16 = AudioStream::allocate();
    if (blockF32) {
        // Change F32 to I16
        for(int i=0; i<128; i++) {
            blockI16->data[i] = (int16_t)(32768.0f*blockF32->data[i]);
        }
        AudioStream_F32::release(blockF32);  // End of F32 activity

        // From here down to end of left channel is the same as for I16 Teensy Audio
        // Now I16, so sort out the DMA data
        __disable_irq();
        if (block_left_1st == NULL) {
            block_left_1st = blockI16;
            block_left_offset = 0;
            __enable_irq();
        } else if (block_left_2nd == NULL) {
            block_left_2nd = blockI16;
            __enable_irq();
        } else {
            audio_block_t *tmp = block_left_1st;
            block_left_1st = block_left_2nd;
            block_left_2nd = blockI16;
            block_left_offset = 0;
            __enable_irq();
            AudioStream::release(tmp);
        }
    }

    blockF32 = AudioStream_F32::receiveReadOnly_f32(1); // input 1 = right
    if (blockF32) {
		for(int i=0; i<128; i++) {
            blockI16->data[i] = (int16_t)(32768.0f*blockF32->data[i]);
        }
        AudioStream_F32::release(blockF32);  // Second end of F32 activity

        __disable_irq();
        if (block_right_1st == NULL) {
            block_right_1st = blockI16;
            block_right_offset = 0;
            __enable_irq();
        } else if (block_right_2nd == NULL) {
            block_right_2nd = blockI16;
            __enable_irq();
        } else {
            audio_block_t *tmp = block_right_1st;
            block_right_1st = block_right_2nd;
            block_right_2nd = blockI16;
            block_right_offset = 0;
            __enable_irq();
            AudioStream::release(tmp);
        }
    }
    AudioStream::release(blockI16);
}  // end update()

#if defined(KINETISK) || defined(KINETISL)
// MCLK needs to be 48e6 / 1088 * 256 = 11.29411765 MHz -> 44.117647 kHz sample rate
//
#if F_CPU == 96000000 || F_CPU == 48000000 || F_CPU == 24000000
  // PLL is at 96 MHz in these modes
  #define MCLK_MULT 2
  #define MCLK_DIV  17
#elif F_CPU == 72000000
  #define MCLK_MULT 8
  #define MCLK_DIV  51
#elif F_CPU == 120000000
  #define MCLK_MULT 8
  #define MCLK_DIV  85
#elif F_CPU == 144000000
  #define MCLK_MULT 4
  #define MCLK_DIV  51
#elif F_CPU == 168000000
  #define MCLK_MULT 8
  #define MCLK_DIV  119
#elif F_CPU == 180000000
  #define MCLK_MULT 16
  #define MCLK_DIV  255
  #define MCLK_SRC  0
#elif F_CPU == 192000000
  #define MCLK_MULT 1
  #define MCLK_DIV  17
#elif F_CPU == 216000000
  #define MCLK_MULT 12
  #define MCLK_DIV  17
  #define MCLK_SRC  1
#elif F_CPU == 240000000
  #define MCLK_MULT 2
  #define MCLK_DIV  85
  #define MCLK_SRC  0
#elif F_CPU == 256000000
  #define MCLK_MULT 12
  #define MCLK_DIV  17
  #define MCLK_SRC  1
#elif F_CPU == 16000000
  #define MCLK_MULT 12
  #define MCLK_DIV  17
#else
  #error "This CPU Clock Speed is not supported by the Audio library";
#endif

#ifndef MCLK_SRC
#if F_CPU >= 20000000
  #define MCLK_SRC  3  // the PLL
#else
  #define MCLK_SRC  0  // system clock
#endif
#endif
#endif

void AudioOutputI2S_OA_F32::config_i2s(void)
{
#if defined(KINETISK) || defined(KINETISL)
    SIM_SCGC6 |= SIM_SCGC6_I2S;
    SIM_SCGC7 |= SIM_SCGC7_DMA;
    SIM_SCGC6 |= SIM_SCGC6_DMAMUX;

    // if either transmitter or receiver is enabled, do nothing
    if (I2S0_TCSR & I2S_TCSR_TE) return;
    if (I2S0_RCSR & I2S_RCSR_RE) return;

    // enable MCLK output
    I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
    while (I2S0_MCR & I2S_MCR_DUF) ;
    I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));

    // configure transmitter
    I2S0_TMR = 0;
    I2S0_TCR1 = I2S_TCR1_TFW(1);  // watermark at half fifo size
    I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
        | I2S_TCR2_BCD | I2S_TCR2_DIV(1);
    I2S0_TCR3 = I2S_TCR3_TCE;
    I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
        | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
    I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);

    // configure receiver (sync'd to transmitter clocks)
    I2S0_RMR = 0;
    I2S0_RCR1 = I2S_RCR1_RFW(1);
    I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
        | I2S_RCR2_BCD | I2S_RCR2_DIV(1);
    I2S0_RCR3 = I2S_RCR3_RCE;
    I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
        | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
    I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);

    // configure pin mux for 3 clock signals
    CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
    CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin  9, PTC3, I2S0_TX_BCLK
    CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK

#elif defined(__IMXRT1062__)

    CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);

    // if either transmitter or receiver is enabled, do nothing
    if (I2S1_TCSR & I2S_TCSR_TE) return;
    if (I2S1_RCSR & I2S_RCSR_RE) return;
//PLL:
    int fs = AUDIO_SAMPLE_RATE_EXACT;
    // PLL between 27*24 = 648MHz und 54*24=1296MHz
    int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
    int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);

    double C = ((double)fs * 256 * n1 * n2) / 24000000;
    int c0 = C;
    int c2 = 10000;
    int c1 = C * c2 - (c0 * c2);
    set_audioClock(c0, c1, c2);

    // clear SAI1_CLK register locations
    CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI1_CLK_SEL_MASK))
           | CCM_CSCMR1_SAI1_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4
    CCM_CS1CDR = (CCM_CS1CDR & ~(CCM_CS1CDR_SAI1_CLK_PRED_MASK | CCM_CS1CDR_SAI1_CLK_PODF_MASK))
           | CCM_CS1CDR_SAI1_CLK_PRED(n1-1) // &0x07
           | CCM_CS1CDR_SAI1_CLK_PODF(n2-1); // &0x3f

    // Select MCLK
    IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1
        & ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK))
        | (IOMUXC_GPR_GPR1_SAI1_MCLK_DIR | IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(0));

    CORE_PIN23_CONFIG = 3;  //1:MCLK
    CORE_PIN21_CONFIG = 3;  //1:RX_BCLK
    CORE_PIN20_CONFIG = 3;  //1:RX_SYNC

    int rsync = 0;
    int tsync = 1;

    I2S1_TMR = 0;
    //I2S1_TCSR = (1<<25); //Reset
    I2S1_TCR1 = I2S_TCR1_RFW(1);
    I2S1_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async;
            | (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1));
    I2S1_TCR3 = I2S_TCR3_TCE;
    I2S1_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF
            | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
    I2S1_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1));

    I2S1_RMR = 0;
    //I2S1_RCSR = (1<<25); //Reset
    I2S1_RCR1 = I2S_RCR1_RFW(1);
    I2S1_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP  // sync=0; rx is async;
            | (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1));
    I2S1_RCR3 = I2S_RCR3_RCE;
    I2S1_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF
            | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
    I2S1_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1));

#endif
}


/******************************************************************/

void AudioOutputI2Sslave_OA_F32::begin(void)
{

    dma.begin(true); // Allocate the DMA channel first

    block_left_1st = NULL;
    block_right_1st = NULL;

    AudioOutputI2Sslave_OA_F32::config_i2s();

#if defined(KINETISK)
    CORE_PIN22_CONFIG = PORT_PCR_MUX(6); // pin 22, PTC1, I2S0_TXD0
    dma.TCD->SADDR = i2s_tx_buffer;
    dma.TCD->SOFF = 2;
    dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
    dma.TCD->NBYTES_MLNO = 2;
    dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
    dma.TCD->DADDR = (void *)((uint32_t)&I2S0_TDR0 + 2);
    dma.TCD->DOFF = 0;
    dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->DLASTSGA = 0;
    dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
    dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_TX);
    dma.enable();

    I2S0_TCSR = I2S_TCSR_SR;
    I2S0_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;

#elif defined(__IMXRT1062__)
    CORE_PIN7_CONFIG  = 3;  //1:TX_DATA0
    dma.TCD->SADDR = i2s_tx_buffer;
    dma.TCD->SOFF = 2;
    dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
    dma.TCD->NBYTES_MLNO = 2;
    dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
    dma.TCD->DOFF = 0;
    dma.TCD->CITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->DLASTSGA = 0;
    dma.TCD->BITER_ELINKNO = sizeof(i2s_tx_buffer) / 2;
    dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2);
    dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
    dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
    dma.enable();

    I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
    I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
#endif

    update_responsibility = update_setup();
    dma.attachInterrupt(isr);
}

void AudioOutputI2Sslave_OA_F32::config_i2s(void)
{
#if defined(KINETISK)
    SIM_SCGC6 |= SIM_SCGC6_I2S;
    SIM_SCGC7 |= SIM_SCGC7_DMA;
    SIM_SCGC6 |= SIM_SCGC6_DMAMUX;

    // if either transmitter or receiver is enabled, do nothing
    if (I2S0_TCSR & I2S_TCSR_TE) return;
    if (I2S0_RCSR & I2S_RCSR_RE) return;

    // Select input clock 0
    // Configure to input the bit-clock from pin, bypasses the MCLK divider
    I2S0_MCR = I2S_MCR_MICS(0);
    I2S0_MDR = 0;

    // configure transmitter
    I2S0_TMR = 0;
    I2S0_TCR1 = I2S_TCR1_TFW(1);  // watermark at half fifo size
    I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP;

    I2S0_TCR3 = I2S_TCR3_TCE;
    I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
        | I2S_TCR4_FSE | I2S_TCR4_FSP;

    I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);

    // configure receiver (sync'd to transmitter clocks)
    I2S0_RMR = 0;
    I2S0_RCR1 = I2S_RCR1_RFW(1);
    I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP;

    I2S0_RCR3 = I2S_RCR3_RCE;
    I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
        | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;

    I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);

    // configure pin mux for 3 clock signals
    CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
    CORE_PIN9_CONFIG  = PORT_PCR_MUX(6); // pin  9, PTC3, I2S0_TX_BCLK
    CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK

#elif defined(__IMXRT1062__)

    CCM_CCGR5 |= CCM_CCGR5_SAI1(CCM_CCGR_ON);

    // if either transmitter or receiver is enabled, do nothing
    if (I2S1_TCSR & I2S_TCSR_TE) return;
    if (I2S1_RCSR & I2S_RCSR_RE) return;

    // not using MCLK in slave mode - hope that's ok?
    //CORE_PIN23_CONFIG = 3;  // AD_B1_09  ALT3=SAI1_MCLK
    CORE_PIN21_CONFIG = 3;  // AD_B1_11  ALT3=SAI1_RX_BCLK
    CORE_PIN20_CONFIG = 3;  // AD_B1_10  ALT3=SAI1_RX_SYNC
    IOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 1; // 1=GPIO_AD_B1_11_ALT3, page 868
    IOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 1; // 1=GPIO_AD_B1_10_ALT3, page 872

    // configure transmitter
    I2S1_TMR = 0;
    I2S1_TCR1 = I2S_TCR1_RFW(1);  // watermark at half fifo size
    I2S1_TCR2 = I2S_TCR2_SYNC(1) | I2S_TCR2_BCP;
    I2S1_TCR3 = I2S_TCR3_TCE;
    I2S1_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
        | I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_RCR4_FSD;
    I2S1_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);

    // configure receiver
    I2S1_RMR = 0;
    I2S1_RCR1 = I2S_RCR1_RFW(1);
    I2S1_RCR2 = I2S_RCR2_SYNC(0) | I2S_TCR2_BCP;
    I2S1_RCR3 = I2S_RCR3_RCE;
    I2S1_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
        | I2S_RCR4_FSE | I2S_RCR4_FSP;
    I2S1_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);

#endif
}