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514 lines
15 KiB
514 lines
15 KiB
// ---------------------------------------------------------------------------
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// This file is part of reSID, a MOS6581 SID emulator engine.
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// Copyright (C) 2004 Dag Lem <resid@nimrod.no>
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ---------------------------------------------------------------------------
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#ifndef __WAVE_H__
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#define __WAVE_H__
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#include "siddefs.h"
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RESID_NAMESPACE_START
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// ----------------------------------------------------------------------------
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// A 24 bit accumulator is the basis for waveform generation. FREQ is added to
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// the lower 16 bits of the accumulator each cycle.
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// The accumulator is set to zero when TEST is set, and starts counting
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// when TEST is cleared.
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// The noise waveform is taken from intermediate bits of a 23 bit shift
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// register. This register is clocked by bit 19 of the accumulator.
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// ----------------------------------------------------------------------------
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class WaveformGenerator
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{
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public:
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WaveformGenerator();
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void set_sync_source(WaveformGenerator*);
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//void set_chip_model(chip_model model);
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RESID_INLINE void clock();
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RESID_INLINE void clock(cycle_count delta_t);
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RESID_INLINE void synchronize();
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void reset();
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void writeFREQ_LO(reg8);
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void writeFREQ_HI(reg8);
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void writePW_LO(reg8);
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void writePW_HI(reg8);
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void writeCONTROL_REG(reg8);
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reg8 readOSC();
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// 12-bit waveform output.
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RESID_INLINE reg12 output();
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protected:
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const WaveformGenerator* sync_source;
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WaveformGenerator* sync_dest;
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// Tell whether the accumulator MSB was set high on this cycle.
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bool msb_rising;
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reg24 accumulator;
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reg24 shift_register;
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// Fout = (Fn*Fclk/16777216)Hz
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reg16 freq;
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// PWout = (PWn/40.95)%
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reg12 pw;
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// The control register right-shifted 4 bits; used for output function
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// table lookup.
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reg8 waveform;
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// The remaining control register bits.
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reg8 test;
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reg8 ring_mod;
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reg8 sync;
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// The gate bit is handled by the EnvelopeGenerator.
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// 16 possible combinations of waveforms.
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RESID_INLINE reg12 output____();
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RESID_INLINE reg12 output___T();
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RESID_INLINE reg12 output__S_();
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RESID_INLINE reg12 output__ST();
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RESID_INLINE reg12 output_P__();
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RESID_INLINE reg12 output_P_T();
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RESID_INLINE reg12 output_PS_();
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RESID_INLINE reg12 output_PST();
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RESID_INLINE reg12 outputN___();
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RESID_INLINE reg12 outputN__T();
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RESID_INLINE reg12 outputN_S_();
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RESID_INLINE reg12 outputN_ST();
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RESID_INLINE reg12 outputNP__();
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RESID_INLINE reg12 outputNP_T();
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RESID_INLINE reg12 outputNPS_();
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RESID_INLINE reg12 outputNPST();
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// Sample data for combinations of waveforms.
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/*
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static reg8 wave6581__ST[];
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static reg8 wave6581_P_T[];
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static reg8 wave6581_PS_[];
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static reg8 wave6581_PST[];
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static reg8 wave8580__ST[];
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static reg8 wave8580_P_T[];
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static reg8 wave8580_PS_[];
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static reg8 wave8580_PST[];
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reg8* wave__ST;
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reg8* wave_P_T;
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reg8* wave_PS_;
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reg8* wave_PST;
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*/
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const reg8* wave__ST;
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const reg8* wave_P_T;
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const reg8* wave_PS_;
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const reg8* wave_PST;
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friend class Voice;
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friend class SID;
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};
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// ----------------------------------------------------------------------------
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// Inline functions.
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// The following functions are defined inline because they are called every
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// time a sample is calculated.
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// ----------------------------------------------------------------------------
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#if RESID_INLINING || defined(__WAVE_CC__)
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// ----------------------------------------------------------------------------
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// SID clocking - 1 cycle.
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// ----------------------------------------------------------------------------
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RESID_INLINE
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void WaveformGenerator::clock()
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{
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// No operation if test bit is set.
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if (test) {
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return;
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}
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reg24 accumulator_prev = accumulator;
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// Calculate new accumulator value;
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accumulator += freq;
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accumulator &= 0xffffff;
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// Check whether the MSB is set high. This is used for synchronization.
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msb_rising = !(accumulator_prev & 0x800000) && (accumulator & 0x800000);
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// Shift noise register once for each time accumulator bit 19 is set high.
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if (!(accumulator_prev & 0x080000) && (accumulator & 0x080000)) {
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reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1;
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shift_register <<= 1;
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shift_register &= 0x7fffff;
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shift_register |= bit0;
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}
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}
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// ----------------------------------------------------------------------------
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// SID clocking - delta_t cycles.
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// ----------------------------------------------------------------------------
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RESID_INLINE
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void WaveformGenerator::clock(cycle_count delta_t)
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{
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// No operation if test bit is set.
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if (test) {
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return;
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}
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reg24 accumulator_prev = accumulator;
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// Calculate new accumulator value;
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reg24 delta_accumulator = delta_t*freq;
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accumulator += delta_accumulator;
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accumulator &= 0xffffff;
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// Check whether the MSB is set high. This is used for synchronization.
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msb_rising = !(accumulator_prev & 0x800000) && (accumulator & 0x800000);
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// Shift noise register once for each time accumulator bit 19 is set high.
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// Bit 19 is set high each time 2^20 (0x100000) is added to the accumulator.
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reg24 shift_period = 0x100000;
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while (delta_accumulator) {
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if (delta_accumulator < shift_period) {
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shift_period = delta_accumulator;
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// Determine whether bit 19 is set on the last period.
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// NB! Requires two's complement integer.
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if (shift_period <= 0x080000) {
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// Check for flip from 0 to 1.
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if (((accumulator - shift_period) & 0x080000) || !(accumulator & 0x080000))
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{
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break;
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}
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}
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else {
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// Check for flip from 0 (to 1 or via 1 to 0) or from 1 via 0 to 1.
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if (((accumulator - shift_period) & 0x080000) && !(accumulator & 0x080000))
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{
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break;
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}
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}
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}
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// Shift the noise/random register.
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// NB! The shift is actually delayed 2 cycles, this is not modeled.
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reg24 bit0 = ((shift_register >> 22) ^ (shift_register >> 17)) & 0x1;
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shift_register <<= 1;
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shift_register &= 0x7fffff;
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shift_register |= bit0;
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delta_accumulator -= shift_period;
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}
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}
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// ----------------------------------------------------------------------------
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// Synchronize oscillators.
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// This must be done after all the oscillators have been clock()'ed since the
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// oscillators operate in parallel.
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// Note that the oscillators must be clocked exactly on the cycle when the
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// MSB is set high for hard sync to operate correctly. See SID::clock().
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// ----------------------------------------------------------------------------
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RESID_INLINE
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void WaveformGenerator::synchronize()
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{
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// A special case occurs when a sync source is synced itself on the same
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// cycle as when its MSB is set high. In this case the destination will
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// not be synced. This has been verified by sampling OSC3.
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if (msb_rising && sync_dest->sync && !(sync && sync_source->msb_rising)) {
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sync_dest->accumulator = 0;
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}
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}
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// ----------------------------------------------------------------------------
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// Output functions.
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// NB! The output from SID 8580 is delayed one cycle compared to SID 6581,
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// this is not modeled.
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// ----------------------------------------------------------------------------
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// No waveform:
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// Zero output.
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//
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RESID_INLINE
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reg12 WaveformGenerator::output____()
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{
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return 0x000;
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}
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// Triangle:
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// The upper 12 bits of the accumulator are used.
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// The MSB is used to create the falling edge of the triangle by inverting
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// the lower 11 bits. The MSB is thrown away and the lower 11 bits are
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// left-shifted (half the resolution, full amplitude).
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// Ring modulation substitutes the MSB with MSB EOR sync_source MSB.
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//
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RESID_INLINE
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reg12 WaveformGenerator::output___T()
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{
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reg24 msb = (ring_mod ? accumulator ^ sync_source->accumulator : accumulator)
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& 0x800000;
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return ((msb ? ~accumulator : accumulator) >> 11) & 0xfff;
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}
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// Sawtooth:
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// The output is identical to the upper 12 bits of the accumulator.
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//
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RESID_INLINE
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reg12 WaveformGenerator::output__S_()
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{
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return accumulator >> 12;
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}
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// Pulse:
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// The upper 12 bits of the accumulator are used.
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// These bits are compared to the pulse width register by a 12 bit digital
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// comparator; output is either all one or all zero bits.
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// NB! The output is actually delayed one cycle after the compare.
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// This is not modeled.
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//
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// The test bit, when set to one, holds the pulse waveform output at 0xfff
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// regardless of the pulse width setting.
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//
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RESID_INLINE
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reg12 WaveformGenerator::output_P__()
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{
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return (test || (accumulator >> 12) >= pw) ? 0xfff : 0x000;
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}
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// Noise:
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// The noise output is taken from intermediate bits of a 23-bit shift register
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// which is clocked by bit 19 of the accumulator.
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// NB! The output is actually delayed 2 cycles after bit 19 is set high.
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// This is not modeled.
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//
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// Operation: Calculate EOR result, shift register, set bit 0 = result.
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//
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// ----------------------->---------------------
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// | |
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// ----EOR---- |
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// | | |
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// 2 2 2 1 1 1 1 1 1 1 1 1 1 |
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// Register bits: 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---
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// | | | | | | | |
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// OSC3 bits : 7 6 5 4 3 2 1 0
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//
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// Since waveform output is 12 bits the output is left-shifted 4 times.
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//
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RESID_INLINE
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reg12 WaveformGenerator::outputN___()
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{
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return
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((shift_register & 0x400000) >> 11) |
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((shift_register & 0x100000) >> 10) |
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((shift_register & 0x010000) >> 7) |
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((shift_register & 0x002000) >> 5) |
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((shift_register & 0x000800) >> 4) |
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((shift_register & 0x000080) >> 1) |
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((shift_register & 0x000010) << 1) |
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((shift_register & 0x000004) << 2);
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}
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// Combined waveforms:
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// By combining waveforms, the bits of each waveform are effectively short
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// circuited. A zero bit in one waveform will result in a zero output bit
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// (thus the infamous claim that the waveforms are AND'ed).
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// However, a zero bit in one waveform will also affect the neighboring bits
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// in the output. The reason for this has not been determined.
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//
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// Example:
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//
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// 1 1
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// Bit # 1 0 9 8 7 6 5 4 3 2 1 0
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// -----------------------
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// Sawtooth 0 0 0 1 1 1 1 1 1 0 0 0
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//
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// Triangle 0 0 1 1 1 1 1 1 0 0 0 0
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//
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// AND 0 0 0 1 1 1 1 1 0 0 0 0
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//
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// Output 0 0 0 0 1 1 1 0 0 0 0 0
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//
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//
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// This behavior would be quite difficult to model exactly, since the SID
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// in this case does not act as a digital state machine. Tests show that minor
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// (1 bit) differences can actually occur in the output from otherwise
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// identical samples from OSC3 when waveforms are combined. To further
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// complicate the situation the output changes slightly with time (more
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// neighboring bits are successively set) when the 12-bit waveform
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// registers are kept unchanged.
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//
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// It is probably possible to come up with a valid model for the
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// behavior, however this would be far too slow for practical use since it
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// would have to be based on the mutual influence of individual bits.
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//
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// The output is instead approximated by using the upper bits of the
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// accumulator as an index to look up the combined output in a table
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// containing actual combined waveform samples from OSC3.
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// These samples are 8 bit, so 4 bits of waveform resolution is lost.
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// All OSC3 samples are taken with FREQ=0x1000, adding a 1 to the upper 12
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// bits of the accumulator each cycle for a sample period of 4096 cycles.
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//
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// Sawtooth+Triangle:
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// The sawtooth output is used to look up an OSC3 sample.
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//
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// Pulse+Triangle:
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// The triangle output is right-shifted and used to look up an OSC3 sample.
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// The sample is output if the pulse output is on.
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// The reason for using the triangle output as the index is to handle ring
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// modulation. Only the first half of the sample is used, which should be OK
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// since the triangle waveform has half the resolution of the accumulator.
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//
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// Pulse+Sawtooth:
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// The sawtooth output is used to look up an OSC3 sample.
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// The sample is output if the pulse output is on.
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//
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// Pulse+Sawtooth+Triangle:
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// The sawtooth output is used to look up an OSC3 sample.
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// The sample is output if the pulse output is on.
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//
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RESID_INLINE
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reg12 WaveformGenerator::output__ST()
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{
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return wave__ST[output__S_()] << 4;
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}
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RESID_INLINE
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reg12 WaveformGenerator::output_P_T()
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{
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return (wave_P_T[output___T() >> 1] << 4) & output_P__();
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}
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RESID_INLINE
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reg12 WaveformGenerator::output_PS_()
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{
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return (wave_PS_[output__S_()] << 4) & output_P__();
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}
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RESID_INLINE
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reg12 WaveformGenerator::output_PST()
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{
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return (wave_PST[output__S_()] << 4) & output_P__();
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}
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// Combined waveforms including noise:
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// All waveform combinations including noise output zero after a few cycles.
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// NB! The effects of such combinations are not fully explored. It is claimed
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// that the shift register may be filled with zeroes and locked up, which
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// seems to be true.
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// We have not attempted to model this behavior, suffice to say that
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// there is very little audible output from waveform combinations including
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// noise. We hope that nobody is actually using it.
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//
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RESID_INLINE
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reg12 WaveformGenerator::outputN__T()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputN_S_()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputN_ST()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputNP__()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputNP_T()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputNPS_()
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{
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return 0;
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}
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RESID_INLINE
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reg12 WaveformGenerator::outputNPST()
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{
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return 0;
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}
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// ----------------------------------------------------------------------------
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// Select one of 16 possible combinations of waveforms.
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// ----------------------------------------------------------------------------
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RESID_INLINE
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reg12 WaveformGenerator::output()
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{
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// It may seem cleaner to use an array of member functions to return
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// waveform output; however a switch with inline functions is faster.
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switch (waveform) {
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default:
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case 0x0:
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return output____();
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case 0x1:
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return output___T();
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case 0x2:
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return output__S_();
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case 0x3:
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return output__ST();
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case 0x4:
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return output_P__();
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case 0x5:
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return output_P_T();
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case 0x6:
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return output_PS_();
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case 0x7:
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return output_PST();
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case 0x8:
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return outputN___();
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case 0x9:
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return outputN__T();
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case 0xa:
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return outputN_S_();
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case 0xb:
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return outputN_ST();
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case 0xc:
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return outputNP__();
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case 0xd:
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return outputNP_T();
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case 0xe:
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return outputNPS_();
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case 0xf:
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return outputNPST();
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}
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}
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#endif // RESID_INLINING || defined(__WAVE_CC__)
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RESID_NAMESPACE_STOP
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#endif // not __WAVE_H__
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