39 lines
1.4 KiB
39 lines
1.4 KiB
#pragma once
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#include "core_pins.h"
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#include <cstdint>
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struct GPIO_Info_t
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{
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inline GPIO_Info_t(unsigned pin);
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const uintptr_t pinCfg;
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const unsigned gpioPortNr;
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const unsigned gpioBitNr;
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char name[20];
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};
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//======================================================================================
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#if defined(KINETISK) || defined(KINETISL)
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GPIO_Info_t::GPIO_Info_t(unsigned pin)
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: pinCfg((uintptr_t)digital_pin_to_info_PGM[pin].config), // address of pin config register
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gpioPortNr((pinCfg - (uintptr_t)&PORTA_PCR0) / 0x1000), // cfg base addresses are 4kB aligned staring with PORTA_PCR0
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gpioBitNr((pinCfg & 0xFFF) / 4) // each bit has to 4 consecutive 32bit cfg registers
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{
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snprintf(name, 20, "GPIO%d_%02d", gpioPortNr, gpioBitNr);
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}
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//======================================================================================
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#elif defined(ARDUINO_TEENSY40) || defined(ARDUINO_TEENSY41)
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GPIO_Info_t::GPIO_Info_t(unsigned pin)
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: pinCfg((uintptr_t)digital_pin_to_info_PGM[pin].reg), // address of pin config register
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gpioPortNr((pinCfg - (uintptr_t)&IMXRT_GPIO6) / 0x4000 + 6), // cfg base addresses are 4kB aligned staring with PORTA_PCR0
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gpioBitNr(__builtin_ffs(digital_pin_to_info_PGM[pin].mask) - 1) // each bit has to 4 consecutive 32bit cfg registers
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{
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snprintf(name, 20, "GPIO%d_%02d", gpioPortNr, gpioBitNr);
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}
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#endif |